Fully configurable ARC processor based hardware and software subsystems reduce SoC design time, lower risk, and accelerate time to market.

The MIPS ARC® HS Development Kits are ready-to-use platforms for rapid software development on the ARC HS3x and HS4x/4xD processor families.

The ARC LC3 codec algorithm is a low complexity communications codec within the Bluetooth standard, to deliver voice and audio streaming.

MIPS ARC® SEM Family of performance-efficient, ultra-low power, compact security processors enables designers to integrate security into their SoCs.

The ARC HS L2 cache option is user configurable from 128KB to 8 MB and can be used with a single-core or multi-core implementation with all CPUs in a multicore cluster sharing the same L2 cache.

Ultra-compact ARC EM processors offer excellent code density, small size, and low power consumption for constrained embedded and deeply embedded applications.

Complete, configurable, extendible and high-performance processors that can easily be incorporated into SoC designs to enable high-quality audio applications.

A high-quality decoder that decodes up to 7.1 channel audio streams according to the AAC LC profiles of the ISO/IEC 14496-3 standard.

The ARC4xD processors feature a dual-issue, 32-bit, RISC + DSP architecture for use in embedded applications where high-performance and high clock speed plus signal processing are required.

The MIPS ARC® HS46FS, HS46FSx4, HS47DFS and HS47DFSx4 functional safety processors simplify development of high-performance safety-critical applications.