MIPS Acies platforms
Bring modern AI models into real-world systems
Inference-native AI acceleration based on open technology
A simple path to modern AI inference
MIPS Acies is a programmable edge AI platform for robotics, intelligent automation, vision systems, and smart devices. MIPS Acies-1 combines standards-based RISC-V compute, an open software environment, virtual development models, and model lowering services into an M.2 PCIe module to help developers move from AI models to efficient local inference.
Efficiency for agentic AI workloads
the tokens per watt of leading AI inference systems
50 TOPS | 10W
8 cores | >50 GB/s
Full Precision
Software-first
The open-source IREE toolchain takes ONNX, PyTorch and TensorFlow models natively
SW/HW Co-design
Atlas Explorer virtual models tune workloads before silicon
Open technology. Practical deployment.
Acies builds on open RISC-V standards and established AI software technologies. This foundation supports software portability, ecosystem reuse, and continued development as models and applications change.
Acies combines programmable scalar, vector, and matrix processing for local AI inference. Developers can evaluate performance using their own models, data sets, precision requirements, latency targets, memory behavior, and power constraints.
MIPS adds the technology and support required for commercial implementation, including model lowering, optimized kernels, runtime integration, workload analysis, virtual-platform access, model enablement, and customer engineering services.
Features
- Acies-1 is an edge accelerator for modern AI
- Native agentic capabilities for robotics and automation devices
- Standards-based: MIPS Atlas S8200
- RVA23 profile with RVV and VME
- Llama.cpp and Qwen for LLMs, plus vision transformers (ViTs) and VLAs
- Atlas SDK and Graph Performance Simulator, with IREE-based MLIR for TensorFlow, PyTorch and ONNX
- Easy-to-integrate M.2 PCIe form factor
Evaluate Acies-1 for your workload with virtual modeling
Block diagram: MIPS Acies-1 SoC
Any performance, power, efficiency, or other product or competitive claims are estimates based on MIPS internal projections and are subject to change. Results may vary based on final product specification, use case, workload, implementation, and other related factors outside of consideration in these statements. Performance depends on the model, data set, numerical format, software optimization, memory behavior, power constraints, and system implementation.
“What has stood out throughout our engagement with MIPS, is how seamlessly the teams worked together to accelerate innovation. By combining Apex’s design expertise with MIPS’ deep implementation capabilities and close alignment with GlobalFoundries, we created a highly collaborative development model that allowed us to move quickly, solve challenges in real time, and streamline the path from FPGA to ASIC. For a startup, that translates directly into preserving resources for the innovation that truly differentiates the product.”
Hasan Unlu
Founder and CEO of Apex Compute
“What stands out in the MIPS+GlobalFoundries Prototype to Product path is the consolidation of three or more vendor relationships into a single accountable partner. For small, architecturally novel teams, that integration is what makes a faster, cheaper, and lower-risk route from FPGA to custom silicon credible rather than aspirational.”