AI / Data Center Infrastructure
Data orchestration and agentic control processors
Power Efficiency and Data Orchestration at Scale
Physical AI systems generate enormous streams of video, lidar, radar, vibration, and telemetry data, and all of it has to move through the edge system fast enough to support real-time decisions. Most of that movement happens between the sensor, the memory, and the AI accelerator, where it consumes the bandwidth and power that thermally and battery-constrained systems can least afford to spend.
In traditional designs: Data-plane tasks (packet forwarding, sensor I/O, accelerator control) run on specialized processors or firmware. Control-plane logic (management, scheduling, OS) runs on a general-purpose CPU. The boundary between the two becomes a bottleneck, especially as edge systems absorb more AI capability. Every hand-off between cores or subsystems adds latency, burns power, and complicates software development.
As data centers face mounting constraints around power and compute, Physical AI helps alleviate this pressure by shifting intelligence and decision-making to the edge directly onto devices, further accelerating this adoption.
Physical AI continuously aggregates data from diverse sensors, processes information at varying levels of fidelity and makes decisions that are executed through motors and actuators in split seconds. These systems also operate across multiple sensor domains, enabling a true form of intelligent autonomy that allows machines to sense, think, act and communicate within the physical world.
MIPS solutions improve efficiency through optimized data management
and near-memory compute
DPU
Data center offload of networking overhead from host processors
Storage
Data center offload of storage overhead from host processors
Communications
5G/6G Infrastructure
Easy to Adopt
- Built on foundation of rapidly embraced, highly flexible, open ISA
- Configurable support for both application and embedded processor use cases
Leading Efficiency
- Tuned performance for highly parallel and data movement functions
- SMT and compact 9-stage microarchitecture for deterministic/low latency task switch
- MIPS Defined Instructions (MDIs) optimizing data movement and distributed processing
Scalable & Configurable Platform
- Designed for multi-cluster implementations for many core and many hart systems
- Flexible feature configurations to support multiple system topologies
Use Cases
Smart NIC / DPU
Integrates control and data planes for packet orchestration, replacing multi-chip designs with a single programmable fabric.
Storage Controller
Handles concurrent I/O paths and AIb-ased caching with consistent response time.