Overview
The MIPS ARC® HS45D and HS47D processors feature a dual-issue, 32-bit, RISC + DSP architecture for use in embedded applications where high-performance and high clock speed plus signal processing are required. The cores can be clocked at up to 1.9 GHz in 16ff processes (worst case, single core, base configuration) and offer outstanding performance delivering 3.0 DMIPS/MHz and 5.2 CoreMark/MHz with a small area footprint and low power consumption.
The processors are based on the advanced ARCv2DSP instruction set architecture (ISA) and pipeline, which provides leading performance-efficiency and code density, and more than 150 DSP instructions. For applications requiring higher performance, dual- and quad-core versions of the HS45D and HS47D cores are available.
The ARC HS45D features close coupled memory (CCM) and is optimized for use in applications where real-time, deterministic behavior is required. The HS47D is designed for high-performance embedded applications that require cache and includes all of the features of the HS45D plus support for up to 64K Level 1 (L1) instruction and data cache.
The processors are designed to be used in applications such as wireless baseband, voice/speech processing, home audio, automotive systems, and other high-end embedded applications that require signal processing.
Highlights
- Combination Dual-issue, 32-bit RISC + DSP processor
- Delivers up to 5700 DMIPS and 9880 CoreMark per core at 1.9 GHz on 16ff (worst case conditions, single-core configuration)
- ARCv2DSP ISA adds over 150 DSP instructions
- Easy DSP programming support with Metaware C/C++ Compiler
- Feature-rich DSP software library for easy algorithm programming
- One 32x32, Two 16x16, or two dual 16x16 MACs/cycle
- Fixed point, vector/SIMD DSP processing support
- Based on advanced ARCv2 ISA
- Support for custom instructions
- Support for up to 16MB of close coupled memory and direct mapping of peripherals
- Dual- and quad-core versions for higher performance
Licensable Options
- Memory Management Unit (MMU)
- L2 Cache
- Floating Point
- Memory Protection
- Mathematical Functions
- Debug
- Cluster DMA
Product Details
Products
| ARC HS45D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions for embedded applications | STARs | Subscribe |
| ARC HS45Dx2 dual-core version of dual-issue HS45D with ARCv2DSP ISA, with 100+ DSP instructions | STARs | Subscribe |
| ARC HS45Dx4 quad-core version of HS45D ARCv2DSP ISA, with 100+ DSP instructions for real-time embedded applications | STARs | Subscribe |
| ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache | STARs | Subscribe |
| ARC HS47Dx2 dual-core version of dual-issue HS47D ARCv2DSP ISA, with 100+ DSP instructions and I&D cache | STARs | Subscribe |
| ARC HS47Dx4 quad-core version of dual-issue HS47D ARCv2DSP ISA, with 100+ DSP instructions and I&D cache | STARs | Subscribe |
Downloads & Documentation
| Description | ARC HS45D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions for embedded applications |
| Name | dwc_arc_hs45d_core |
| Version | 4.10a |
| ECCN | 3E991/NLR |
| STARs | Open and/or Closed STARs |
| myDesignWare | Subscribe for Notifications |
| Product Type | DesignWare Cores |
| Documentation |
Application Notes ARC HS4x Halt on Reset Behavior ( PDF )
Databook ARC HS APEX Databook (4.10a) ( PDF )
ARC HS4x Series Databook (4.10a) ( PDF )
ARC HS4x Series Databook (Beta) ( PDF )
ARC Trace Databook (4.10a) ( PDF )
ARC Trace Databook (Beta) ( PDF )
DSP Library Performance Databook for ARC HS (latest) ( PDF )
HAPS Reference Design Flow Databook (4.10a) ( PDF )
Datasheet MIPS ARC HS4xD Datasheet ( PDF )
Implementation Guide ARC HS4x Implementation and Integration Guide (4.10a) ( PDF )
ARC HS4x Implementation and Integration Guide (Beta) ( PDF )
Reference Manual ARCv2 FPGA Synthesis Flow (4.10a) ( PDF )
ARCv2 ISA Programmer's Reference Manual for ARC HS3x and 4x Processors (Public Edition) ( PDF )
ARCv2 ISA Programmer's Reference Manual for ARC HS4x Processors (4.10a) ( PDF )
User Guide ARC MIPS ASIC Reference Design Flow User's Guide (4.10a) ( PDF )
|
| Toolsets | Qualified Toolsets |
| Download | dwc_arc_hs45d_core |
| Product Code | C247-0 |
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