P8700 Series

High-Performance Multi-Core

  • High-performance compute with simultaneous multi-threading (SMT)
  • 4-issue, 16-stage out-of-order pipeline with 1- or 2-way SMT
  • RISC-V Compliant ISA
    • RV64GHZ + Bitmanip Zba and Zbb, + CMO Extension
    • MIPS User-Defined Instructions (UDI)—Cache and TLB management, Performance enhancements and DVM (Distributed Virtual Memory) support

Coherence Manager

  • Support for up to 8 Coherent initiators comprising of either MIPS RISC-V Processors or 3rd party accelerators
  • Cluster Level-2 Cache L2$ up to 8MB
    • HW pre-fetch, widened busses, reduced latency
  • System interface:
    • ACE or AXI: 256-bit system bus
    • Optional: Non-coherent periphery bus (up to 4-ports)
8700 02

Design and Innovate with MIPS Today

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