Extreme Edge AI Efficiency with RISC-V
In this episode, Sally talks to Manoj Koul about how workload-first, programmable platforms are reshaping compute for Physical AI.
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MIPS and Xcelsa Collaborate to Accelerate Verified, Workload-Optimized Custom Silicon
SAN JOSE, CA. – September 29, 2026 — MIPS, by GF (MIPS), a leading technology provider for efficient workload-focused platforms based on open technology, today announced a strategic non-exclusive partnership with Xcelsa Labs to make custom-chip design more accessible and accelerate the development of application-specific silicon through Xcelsa’s verified compute intelligence platform.
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SystemChat: Let’s Chat about Software Development
On this episode of SystemChat, we hear from our guest Cheol Kim, Director, Business Development at MIPS, and we discuss systems of Software-first Development.
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For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of Choice
I have spent much of my career at the point at which processors, software, and automotive systems converge. Today, that intersection matters more than ever.
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MIPS Launches Workload-Native Platforms for Physical AI
Inference-Native: MIPS Acies™ is an AI inference developer platform for modern edge workloads, with an open, standards-based NPU, an open software stack, and an easy-to-adopt form factor. Event-Native: MIPS Actus™ is a real-time developer platform for event-driven embedded applications such as motion control, sensor fusion, and predictive maintenance. Safety-Native: MIPS Aegis™ is developer platform for
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MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
MIPS combines foundry scale, processor IP, software-first design tools, and open standards leadership to help customers build workload-optimized computing platforms for AI beyond the data center SAN JOSE, CA. – August 27, 2026 – MIPS, by GF, today announced it is now a Premier Member of RISC-V International, with Yankin Tanurhan, SVP & CTO of
AI-era chips will be defined by custom compute, memory proximity, efficiency: Executives
At the ETElectronicsWorld Design & Verification Summit 2026 in Bengaluru, semiconductor leaders said the next wave of AI compute will move towards workload-specific silicon, edge intelligence, advanced packaging and AI-assisted design, while power, memory movement and system-level skills emerge as critical constraints.
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How MIPS Is Powering Physical AI with RISC-V and Software-to-Silicon Development
MIPS, by GlobalFoundries, is an early pioneer of the original reduced instruction set revolution and is now focused on enabling Physical AI systems with the modern, open RISC-V instruction set architecture.
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