MIPS Launches Workload-Native Platforms for Physical AI
- September 2, 2026
Inference-Native: MIPS Acies™ is an AI inference developer platform for modern edge workloads, with an open, standards-based NPU, an open software stack, and...
MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- August 27, 2026
MIPS combines foundry scale, processor IP, software-first design tools, and open standards leadership to help customers build workload-optimized computing platforms for AI...
GlobalFoundries completes acquisition of Synopsys’ Processor IP Solutions Business, delivering a holistic technology platform for Physical AI
- June 2, 2026
Combines GF’s Physical AI portfolio with MIPS’ RISC-V and software-to-silicon expertise to accelerate custom, software-first products for automotive, industrial and agentic edge platforms...
MIPS and INOVA Collaborate to put Physical AI into the palm of Robotic hands with new Reference Platform
- March 9, 2026
Inova Semiconductors collaborate with MIPS to build reference Physical AI platform for secure architectures in Robotics applications New platform will be a hardware-based...
MIPS and Green Hills Software Accelerate Safety Certified Product Development for MIPS RISC-V Microcontrollers
- March 9, 2026
Collaboration accelerates time-to-market for mission-critical applications in automotive and industrial markets Designed for real-time, event-driven Physical AI action platforms that need safety certification...
GlobalFoundries to Acquire Synopsys’ Processor IP Solutions Business, Expanding Capabilities to Accelerate Physical AI Applications
- January 14, 2026
Acquisition will strengthen GF’s leadership in Physical AI, enhances compute capabilities, expands company’s RISC-V and AI portfolio and software tools and accelerates custom...
MIPS S8200 Delivers Software-First RISC-V NPU To Enable Physical AI at the Autonomous Edge
- January 5, 2026
MIPS S8200 NPU is sampling now to lead customers developing autonomous edge transportation, robotics, and embedded platforms ForwardEdge ASIC selects MIPS S8200 NPU...
Siemens and GlobalFoundries collaborate to deploy AI-driven manufacturing to strengthen global semiconductor supply
- December 11, 2025
Strategic collaboration to enhance performance of semiconductors and other advanced industries based on both companies’ AI-based capabilities Centralized AI-enabled automation, predictive maintenance, advanced...
Quintauris Announces Strategic Collaboration with MIPS to enable MIPS Atlas as part of RT-Europa
- December 10, 2025
Quintauris, a leading provider of RISC-V solutions, and MIPS, a GlobalFoundries company and leading provider of RISC-V IP and software for physical AI...
MIPS I8500 Processor Orchestrates Data Movement for the AI Era
MIPS I8500 delivers deterministic, secure data orchestration for Physical AI with 3rd generation four-thread-per-core processor built using open RISC-V ISA SAN JOSE, Calif.,...
MIPS Appoints Moshe Hillel to Accelerate Growth in Israel
- October 13, 2025
MIPS business development in Israel will drive Automotive, Industrial, Data Center Infrastructure, and Communications Infrastructure market growth, fueled by the open and modular...
MIPS Appoints Alan Li as Head of Business Development to Accelerate China Growth
- September 22, 2025
MIPS China business development team has strong focus on Automotive, Industrial, and Communications Infrastructure market growth, leveraging the industry-leading MIPS Atlas Portfolio of...
Linux 6.7 release – Main changes, Arm, RISC-V, and MIPS architectures
- January 8, 2024
So we had a little bit more going on last week compared to the holiday week before that, but certainly not enough to...
CEO interview: MIPS’ Sameer Wasson on a RISC-V reboot
- January 5, 2024
MIPS Inc. is emerging as a significant RISC-V processor core licensor under its recently-appointed CEO Sameer Wasson. eeNews Europe interviewed Wasson to find...
MIPS recruits former senior SiFive execs to boost RISC-V play
- January 4, 2024
MIPS Inc. (San Jose, Calif.) has recruited Drew Barbier and Brad Burgess to its leadership team, both formerly with RISC-V pioneer SiFive Inc....
Chip company MIPS poaches two SiFive execs for leadership team
- January 4, 2024
Two former SiFive executives have joined the executive leadership team of semiconductor design company MIPS. MIPS, a company focused on the development of...
MIPS snags top SiFive brains to amp up RISC-V business
- January 3, 2024
Chip designer MIPS has picked up two former execs from SiFive in a bid to boost its RISC-V development efforts. MIPS, the company...
MIPS Welcomes New Executives as Part of Company’s Growth and Expansion
- January 3, 2024
MIPS, a leading developer of high- performance RISC-V compute IP, today announced the addition of two semiconductor industry veterans to its leadership team....
MIPS Inc. Boosts Leadership Team, Eyes RISC-V Market Expansion
- January 3, 2024
In a strategic move poised to invigorate the RISC architecture processors domain, MIPS Inc., a groundbreaking company in the sector, has announced the...
Sameer Wasson’s Vision for MIPS/RISC-V
- December 14, 2023
MIPS, a storied CPU IP core company with a tortuous business/management history, is writing a new chapter under the watch of new CEO...
China Deploys Massive RISC-V Server in Commercial Cloud
- November 8, 2023
If the U.S. government intends to curb China’s adoption of emerging RISC-V architecture to develop homegrown chips, it may be getting late. Last...
Embedded Computing Design: MIPS Plans Expansion, Pulls New CEO from TI
- September 6, 2023
The recent growth in RISC-V interest and adoption is hard to deny, and MIPS, a developer of high-performance RISC-V compute IP, is looking...
MIPS taps Siemens FPGA for RISC-V CPU roll out
- May 30, 2023
MIPS is using an FPGA platform from Siemens Digital Industries Software to accelerate software development for its eVocore P8700 RISC-V multiprocessor.
...
Electronic Engineering: MIPS Rolls Out Its First RISC-V Processor Core
- January 9, 2023
Even though the company had telegraphed its big move, MIPS’s adoption of the RISC-V ISA for its future processor cores hit me like...