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MIPS To Showcase New Embedded and Edge AI Innovations At Computex 2024

MIPS, a leading developer of efficient and configurable IP compute cores, will showcase the company’s latest innovations and suite of system deployments

MIPS Continues To Expand With The Addition Of Industry Leaders from NVIDIA, Google and SiFive

Executives’ Technical Prowess Will Help Drive Innovation and Accelerate Product Development to Meet Customer Demand for AI Compute and RISC-V SAN JOSE,

MIPS Expands RISC-V Ecosystem Support to Enable Early Software Development for Multi-threaded Cores

Live Demonstration of Synopsys ImperasFPM Models for MIPS Processors at Embedded World 2024 Showcases Collaboration for RISC-V-Based Designs SAN JOSE, CA –

MIPS Expands Global Footprint with New Design Center and Talent for Systems Architects and AI Compute

MIPS, a leading developer of efficient and configurable compute cores, today announced the company’s global expansion with the launch of a new

MIPS Launches New Corporate Brand At CES 2024

Rebrand Reflects the Company’s Strategic Focus on Giving Customers the Freedom to Innovate Compute in the Automotive, Data Center and Embedded Markets.

MIPS: Freedom to Innovate Compute

Watch the Video: At MIPS, we are giving our customers the freedom to innovate compute in the automotive, data center and embedded

MIPS Welcomes New Executives as Part of Company’s Growth and Expansion

Former SiFive Leaders to Help Drive IP Innovation and Market Penetration SAN JOSE, CA – January 03, 2024 – MIPS, a leading

MIPS Takes Top Honors at Embedded World for eVocore P8700 Multiprocessor

Company’s First RISC-V Product Paves Way for Future of Chip Development   SAN JOSE, Calif., March 16, 2023 /PRNewswire/ — MIPS, a

MIPS Leverages Siemens’ Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor

New Platform to Accelerate Time-to-Market and Reduce Costs & Bottlenecks for SoC Developers   SAN JOSE, Calif., May 30, 2023 /PRNewswire/ —

Imperas Collaborates with MIPS and Ashling to Accelerate RISC-V Application Software Development from SoC Concept to Deployment

Oxford, United Kingdom – March 13th, 2023 – Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced with

MIPS Named Embedded Award Nominee for eVocore P8700 Multiprocessor

Prestigious Global Industry Accolades Honor Top Embedded Systems Innovations SAN JOSE, Calif., Feb. 28, 2023 — MIPS, a leading developer of highly

MIPS Announces Availability of its first RISC-V IP core – the eVocore P8700 Multiprocessor

Industry’s Highest Performance, Most Scalable RISC-V IP Core Already Adopted for Next-Generation Automotive Applications San Jose, Calif., Dec. 12, 2022 — As

Design & Reuse: RISC-V Sees Significant Growth and Technical Progress in 2022 with Billions of RISC-V Cores in Market

Members across the ecosystem have continued to innovate with cutting-edge RISC-V hardware and software solutions. MIPS announced the availability of its first

Tech Insights: MIPS Releases First RISC-V CPUs

MIPS has developed its first licensable CPUs implementing the RISC-V instruction set by repurposing older MIPS-compatible cores. The P8700 and I8500 outperform

MIPS pivots to RISC-V, targets high performance processing

With its transition to RISC-V, MIPS is targeting the high-performance segment of the processor market, leveraging its differentiation in real-time features

EENews Europe: MIPS Previews its Pivot to RISC-V

MIPS is showing the first results of its pivot to the RISC-V architecture following the collapse of Wave Computing.

New Electronics: MIPS enters RISC-V market with eVocore product line-up

MIPS, a developer of RISC processor IP, is entering into the RISC-V market and has offered previews of its first products in

CNX Software: MIPS unveils RISC-V eVocore P8700 and I8500 multiprocessor IP cores

MIPS is dead, right? Well, there’s now very little done on the architecture itself, MIPS (the company) has decided to switch to

HPC Wire: MIPS Pivots to RISC-V with Performance and Scalability

SAN JOSE, Calif., May 10, 2022 — MIPS, a leading developer of highly scalable RISC processor IP, announces its entrance to the

Phoronix: MIPS Claims “Best-In-Class Performance” with New RISC-V eVocore CPUs

MIPS Tech is no longer working on their MIPS CPU instruction set architecture but has been taking on RISC-V based designs. Today

Gaming Info Tech: MIPS Claims “Greatest-In-Class Efficiency” With New RISC-V eVocore CPUs

MIPS Tech is now not engaged on their MIPS CPU instruction set structure however has been taking up RISC-V based mostly designs.

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