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MIPS Releases P8700, Industry’s First High-Performance AI-Enabled RISC-V Automotive CPU for ADAS and Autonomous Vehicles

MIPS, a leading developer of efficient and configurable IP compute cores, will showcase the company’s latest innovations and suite of system deployments at...

MIPS To Showcase New Embedded and Edge AI Innovations At Computex 2024

MIPS, a leading developer of efficient and configurable IP compute cores, will showcase the company’s latest innovations and suite of system deployments at...

MIPS Continues To Expand With The Addition Of Industry Leaders from NVIDIA, Google and SiFive

Executives’ Technical Prowess Will Help Drive Innovation and Accelerate Product Development to Meet Customer Demand for AI Compute and RISC-V SAN JOSE, CA...

MIPS Expands RISC-V Ecosystem Support to Enable Early Software Development for Multi-threaded Cores

Live Demonstration of Synopsys ImperasFPM Models for MIPS Processors at Embedded World 2024 Showcases Collaboration for RISC-V-Based Designs SAN JOSE, CA – April...

MIPS Expands Global Footprint with New Design Center and Talent for Systems Architects and AI Compute

MIPS, a leading developer of efficient and configurable compute cores, today announced the company’s global expansion with the launch of a new R&D...

MIPS Launches New Corporate Brand At CES 2024

Rebrand Reflects the Company’s Strategic Focus on Giving Customers the Freedom to Innovate Compute in the Automotive, Data Center and Embedded Markets. SAN...

MIPS: Freedom to Innovate Compute

Watch the Video: At MIPS, we are giving our customers the freedom to innovate compute in the automotive, data center and embedded markets:...

MIPS Welcomes New Executives as Part of Company’s Growth and Expansion

Former SiFive Leaders to Help Drive IP Innovation and Market Penetration SAN JOSE, CA – January 03, 2024 – MIPS, a leading developer...

MIPS Takes Top Honors at Embedded World for eVocore P8700 Multiprocessor

Company’s First RISC-V Product Paves Way for Future of Chip Development   SAN JOSE, Calif., March 16, 2023 /PRNewswire/ — MIPS, a leading...

MIPS Leverages Siemens’ Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor

New Platform to Accelerate Time-to-Market and Reduce Costs & Bottlenecks for SoC Developers   SAN JOSE, Calif., May 30, 2023 /PRNewswire/ — MIPS,...

Imperas Collaborates with MIPS and Ashling to Accelerate RISC-V Application Software Development from SoC Concept to Deployment

Oxford, United Kingdom – March 13th, 2023 – Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced with MIPS...

MIPS Named Embedded Award Nominee for eVocore P8700 Multiprocessor

Prestigious Global Industry Accolades Honor Top Embedded Systems Innovations SAN JOSE, Calif., Feb. 28, 2023 — MIPS, a leading developer of highly scalable...

MIPS RISC-V ecosystem supports early software development

MIPS has announced that it has expanded its collaboration with Synopsys to accelerate ecosystem enablement of MIPS RISC-V IP and their customer’s ability...

Chip Industry Week In Review

The Japanese government approved $3.9 billion in funding for chipmaker Rapidus to expand its foundry business, of which 10% will be invested in...

MIPS Expands RISC-V Ecosystem Support to Enable Early Software Development for Multi-threaded Cores

MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc. to...

MIPS Expands Global Footprint with New Design Center and Talent for Systems Architects and AI Compute

MIPS, a leading developer of efficient and configurable compute cores, today announced the company’s global expansion with the launch of a new R&D...

RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA

RISC-V, the groundbreaking open and customizable instruction set architecture (ISA), is transforming the world of microprocessors. Its exceptional flexibility empowers developers to craft...

What’s the Difference Between Conventional Memory Protection and CHERI?

Memory safety problems, particularly when it comes to unsafe usage of pointers, are widespread and can cause significant security breaches. and consequent economic...

MIPS Aims to Give Back Control, for AI-Centric Compute

MIPS this week used CES 2024 to announce its new strategic focus and at the same time rebrand, under a mission to “give...

Another Major Player Shakes Up the RISC-V Arena

MIPS has been known for delivering low-power, high-performance embedded processor designs, but its MIPS architecture has been eclipsed by other RISC architectures like...

CES: MIPS CEO Sameer Wasson sees RISC-V as path to freedom

Sameer Wasson is passionate about RISC-V architecture and recently became CEO of MIPS to show the world how important an architecture it is....

Why is MIPS Putting its Primary Focus on RISC-V?

MIPS has been know for delivering low power, high performance embedded processor designs but its MIPS architecture has been eclipsed by other RISC...

Is MIPS Poised to Take the RISC-V World by Storm?

Sometimes the world can be a funny old place. Take computer companies, for example. Some (like IBM) seem to have been around forever,...

China Is All In on a RISC-V Future

The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The...

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