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MIPS Named Embedded Award Nominee for eVocore P8700 Multiprocessor

Prestigious Global Industry Accolades Honor Top Embedded Systems Innovations SAN JOSE, Calif., Feb. 28, 2023 — MIPS, a leading developer of highly scalable...

MIPS Announces Availability of its first RISC-V IP core – the eVocore P8700 Multiprocessor

Industry’s Highest Performance, Most Scalable RISC-V IP Core Already Adopted for Next-Generation Automotive Applications San Jose, Calif., Dec. 12, 2022 — As the...

MIPS Partners With Mobileye to Accelerate Next Generation Autonomous Driving Technologies and Advanced Driver Assistance Systems

Mobileye Adopts New MIPS eVocore RISC-V CPUs; RISC-V Architecture to Help Drive Future of Vehicle Safety San Jose, Calif., December 12, 2022- MIPS,...

MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors

Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models, Verification...

We’re Getting Ready to Launch Something Big at RISC-V Summit 2022!

RISC-V Summit has always been the ideal venue to unveil new innovations that drive higher performance and greater scalability for today’s complex applications....

Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V

Architecture Will Accelerate Innovation in Open Computing SAN JOSE, Calif., Aug. 30, 2022 /PRNewswire/ — MIPS, a leading developer of highly scalable RISC...

MIPS is thrilled to be part of Imperas’ Open Standard RISC-V Verification Interface (RVVI)

July 11th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface)...

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability

Previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors SAN JOSE, Calif. – May 10, 2022 – MIPS,...

MIPS chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA compatible IP cores

SILICON VALLEY, CA, USA – March 28, 2022. Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS...

MIPS selects Imperas Reference Models for RISC-V Processor Verification

Oxford, United Kingdom – November 29th, 2021 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the...

Restructured Wave Computing/MIPS Business Moves ahead as MIPS

SANTA CLARA, Calif., March 1, 2021 /PRNewswire/ — Wave Computing, Inc. (“Wave”) and its subsidiaries including MIPS Tech, the processor technology company focused...

MIPS launches Atlas chip designs for industrial robots and autonomous cars

MIPS is launching its Atlas chip designs for physical AI platforms such as industrial robots and autonomous cars....

MIPS Takes System-Level Approach to Physical AI

MIPS has today introduced its MIPS Atlas portfolio, a product suite comprising compute subsystems and software platform to develop autonomous edge solutions addressing...

Compute subsystems bring real-time intelligence to AI platforms

MIPS has unveiled the MIPS Atlas portfolio of compute subsystems, designed to empower leading automotive, industrial, and embedded technology companies to deploy safe,...

MIPS shifts strategy toward robots and designing chips

MIPS, a decades-old Silicon Valley company that once competed directly with Arm Holdings (O9Ty.F), opens new tab in providing a computing architecture, said...

MIPS: Enabling Tech-Driven Recovery Across Key Industries

As analysts anticipate a gradual recovery of the global economy in 2025, technology will play a critical role....

MIPS at 40

MIPS is celebrating its 40th anniversary as a compute IP company this year. Known for a RISC instruction set, the company has risen...

Not All RISC-V IP is the Same

MIPS CEO Sameer Wasson discusses the company’s approach to RISC-V and how its P8700 RISC-V cores stack up against the competition....

Multicore RISC-V Designs for Smart Automotive Apps

A cluster of six MIPS P8700 RISC-V cores can be replicated up to 64 times to support 768 execution threads....

AI-Enabled RISC-V Cores Target ASIL B Automotive Apps

The MIPS P8700 RISC-V core, which implements a RISC-V ISA, aims at ASIL B and ISO 26262 functional safety....

MIPS releases RISC-V CPU for autonomous vehicles

MIPS released its P8700 CPU based on the RISC-V computing architecture to target driver assistance and autonomous vehicle applications....

Addressing AI While Keeping the MIPSiness In MIPS

MIPS, now targeting AI applications for its application-specific data movement cores, is evolving with a careful eye on its strengths....

Sameer Wasson: Have a Steady Hand, Don’t be Distracted

In this episode of Silicon Grapevine, we talk to MIPS CEO Sameer Wasson about the experience of going from an intern doing FPGA...

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