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MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors

Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models,

We’re Getting Ready to Launch Something Big at RISC-V Summit 2022!

RISC-V Summit has always been the ideal venue to unveil new innovations that drive higher performance and greater scalability for today’s complex

Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V

Architecture Will Accelerate Innovation in Open Computing SAN JOSE, Calif., Aug. 30, 2022 /PRNewswire/ — MIPS, a leading developer of highly scalable

MIPS is thrilled to be part of Imperas’ Open Standard RISC-V Verification Interface (RVVI)

July 11th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability

Previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors SAN JOSE, Calif. – May 10, 2022 –

MIPS chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA compatible IP cores

SILICON VALLEY, CA, USA – March 28, 2022. Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support

MIPS selects Imperas Reference Models for RISC-V Processor Verification

Oxford, United Kingdom – November 29th, 2021 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc.,

Restructured Wave Computing/MIPS Business Moves ahead as MIPS

SANTA CLARA, Calif., March 1, 2021 /PRNewswire/ — Wave Computing, Inc. (“Wave”) and its subsidiaries including MIPS Tech, the processor technology company

Embedded Quest at Embedded World

In our quest for "useful" embedded systems, the Ojo-Yoshida Report roamed the show floor at Embedded World, cornering vendors and asking two

MIPS Adds 3 Managers from NVIDIA, Google and SiFive

MIPS, a developer of efficient and configurable IP compute cores, today announced the addition of three technology and semiconductor industry professionals dedicated

MIPS Expands RISC-V Ecosystem Support to to Enable Early Software Development for Multi-threaded Cores

MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc.

MIPS RISC-V ecosystem supports early software development

MIPS has announced that it has expanded its collaboration with Synopsys to accelerate ecosystem enablement of MIPS RISC-V IP and their customer’s

Chip Industry Week In Review

The Japanese government approved $3.9 billion in funding for chipmaker Rapidus to expand its foundry business, of which 10% will be invested

MIPS Expands RISC-V Ecosystem Support to Enable Early Software Development for Multi-threaded Cores

MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc.

MIPS Expands Global Footprint with New Design Center and Talent for Systems Architects and AI Compute

MIPS, a leading developer of efficient and configurable compute cores, today announced the company’s global expansion with the launch of a new

RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA

RISC-V, the groundbreaking open and customizable instruction set architecture (ISA), is transforming the world of microprocessors. Its exceptional flexibility empowers developers to

What’s the Difference Between Conventional Memory Protection and CHERI?

Memory safety problems, particularly when it comes to unsafe usage of pointers, are widespread and can cause significant security breaches. and consequent

MIPS Aims to Give Back Control, for AI-Centric Compute

MIPS this week used CES 2024 to announce its new strategic focus and at the same time rebrand, under a mission to

Another Major Player Shakes Up the RISC-V Arena

MIPS has been known for delivering low-power, high-performance embedded processor designs, but its MIPS architecture has been eclipsed by other RISC architectures

CES: MIPS CEO Sameer Wasson sees RISC-V as path to freedom

Sameer Wasson is passionate about RISC-V architecture and recently became CEO of MIPS to show the world how important an architecture it

Unlocking the Power of Edge AI Through Efficient Data Movement

By Dave Bell, Senior Director of Product Management, MIPS In today’s interconnected world, the advancement of Edge AI has revolutionized the way

MIPS Launches New Strategic Focus and ReBrand: The Freedom to Innovate Compute

By Sameer Wasson, CEO Today is an exciting day at MIPS as we launch a rebrand and strategic focus on giving our

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