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MIPS Expands RISC-V Ecosystem Support to Enable Early Software Development for Multi-threaded Cores

April 4, 2024
Global network technology

Live Demonstration of Synopsys ImperasFPM Models for MIPS Processors at Embedded World 2024 Showcases Collaboration for RISC-V-Based Designs

SAN JOSE, CA – April 04, 2024 – MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc. to accelerate ecosystem enablement of MIPS RISC-V IP and their customer’s ability to innovate compute without constraints. MIPS will showcase MIPS’ RISC-V IP Core technology utilizing the Synopsys® ImperasFPM Fast Processor Models and the Synopsys ImperasPDK Processor Development Kit software simulation tools at embedded world 2024.

The MIPS RISC-V P8700 IP featured in the demo at embedded world, is a versatile processor, available in scalable multicore configurations, capable of running Linux and other high-level operating systems (HLOS) and is suitable for a variety of automotive (and non-automotive) applications. As a key benefit, customers using the Synopsys ImperasFPM and ImperasPDK fast simulation solution can get started early with software development for the MIPS P8700 and I8500.

“We are pleased to have strengthened our longstanding relationship with Synopsys, and to be demonstrating our innovative RISC-V products at embedded world,” said Drew Barbier, Vice President of Products, MIPS. “Our collaboration with Synopsys marks an important milestone for the company as we showcase our multithreading capabilities, enabling our customers to use the industry leading ImperasFPM RISC-V models and fast simulation tools to develop innovative and differentiated products.”

As part of its activities at embedded world 2024, MIPS will feature a “Synopsys Simulation Model Demonstration” showcasing MIPS’ multithreaded P8700 Series CPU running on Synopsys’ fast simulation tools in MIPS booth (stand 4-470) and the RISC-V International Pavilion. This demo will showcase real-time system deployments, as well as the ability to deliver leading RISC-V tools that accelerate compute innovation.

“High quality processor models are needed in the RISC-V ecosystem to enable early software development,” said Simon Davidmann, Vice President, Engineering in the Systems Design Group, Synopsys. “Our collaboration with MIPS enables customers to accelerate their RISC-V software development and functional verification of advanced SoCs using Synopsys’ leading high-performance ImperasFPM models.”

For close to two decades, MIPS has established a leading position with its deep technical expertise and intellectual property (IP). Today, the company is building off this innovation and expertise to give customers the freedom to build unique products for specific workloads utilizing MIPS’ industry-leading cores.

P8700 and I8500 development kits are currently available to purchase from MIPS. For additional information about MIPS, please visit

About MIPS

MIPS is accelerating compute density in the automotive, cloud and embedded markets. Giving customers the freedom to build unique products for specific workloads, MIPS’ industry-leading cores are configurable, efficient and easy to implement. Its multi-threading methodology delivers advanced scalability and the ability to efficiently move and process data faster. The company’s compute DNA spans three decades with billions of MIPS-based chips shipped to date. For more information, visit


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MIPS Expands Global Footprint with New Design Center and Talent for Systems Architects and AI Compute

MIPS, a leading developer of efficient and configurable compute cores, today announced the company’s global expansion with the launch of a new R&D center in Austin, TX, making this the second office expansion in Texas after Dallas. MIPS plans to tap into the growing AI engineering talent in Texas and continue to build deeper roots in the community by partnering with local universities and schools.

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MIPS Expands RISC-V Ecosystem Support to Enable Early Software Development for Multi-threaded Cores

April 4, 2024
Global network technology

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