Memory safety problems, particularly when it comes to unsafe usage of pointers, are widespread and can cause significant security breaches. and consequent economic damage. CHERI provides a hardware solution by offering fine-grained memory protection.

MIPS this week used CES 2024 to announce its new strategic focus and at the same time rebrand, under a mission to “give back control” to designers looking to differentiate their compute architectures in a new AI-centric world, using the inherent benefits of the RISC-V architecture to enable that.

MIPS has been known for delivering low-power, high-performance embedded processor designs, but its MIPS architecture has been eclipsed by other RISC architectures like Arm and lately RISC-V. RISC-V developers are now MIPS’s target audience thanks to its RISC-V-based platforms. I talked with MIPS CEO, Sameer Wasson, about where MIPS is headed (see video above).

Sameer Wasson is passionate about RISC-V architecture and recently became CEO of MIPS to show the world how important an architecture it is. He uses words like “freedom” when talking about how MIPS and RISC-V can change how developers view the coming demands on software, especially as cars become software defined and where over-the-air updates

MIPS has been know for delivering low power, high performance embedded processor designs but its MIPS architecture has been eclipsed by other RISC architectures like Arm and lately RISC-V. RISC-V developers are now MIPS target audience as its primary platforms are now RISC-V-based.

Sometimes the world can be a funny old place. Take computer companies, for example. Some (like IBM) seem to have been around forever, and they also seem destined to stay around forever.

The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled “Examining China’s Grand Strategy For RISC-V” is part of their China Brief segment and leans on the security concerns of RISC-V.