MIPS Leverages Siemens’ Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor
- May 30, 2023
New Platform to Accelerate Time-to-Market and Reduce Costs & Bottlenecks for SoC Developers SAN JOSE, Calif., May 30, 2023 /PRNewswire/ — MIPS,...
Imperas Collaborates with MIPS and Ashling to Accelerate RISC-V Application Software Development from SoC Concept to Deployment
- March 13, 2023
Oxford, United Kingdom – March 13th, 2023 – Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced with MIPS...
MIPS Named Embedded Award Nominee for eVocore P8700 Multiprocessor
- February 28, 2023
Prestigious Global Industry Accolades Honor Top Embedded Systems Innovations SAN JOSE, Calif., Feb. 28, 2023 — MIPS, a leading developer of highly scalable...
MIPS Announces Availability of its first RISC-V IP core – the eVocore P8700 Multiprocessor
- December 12, 2022
Industry’s Highest Performance, Most Scalable RISC-V IP Core Already Adopted for Next-Generation Automotive Applications San Jose, Calif., Dec. 12, 2022 — As the...
MIPS Partners With Mobileye to Accelerate Next Generation Autonomous Driving Technologies and Advanced Driver Assistance Systems
- December 12, 2022
Mobileye Adopts New MIPS eVocore RISC-V CPUs; RISC-V Architecture to Help Drive Future of Vehicle Safety San Jose, Calif., December 12, 2022- MIPS,...
MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors
- December 7, 2022
Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models, Verification...
We’re Getting Ready to Launch Something Big at RISC-V Summit 2022!
- December 6, 2022
RISC-V Summit has always been the ideal venue to unveil new innovations that drive higher performance and greater scalability for today’s complex applications....
Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V
- August 30, 2022
Architecture Will Accelerate Innovation in Open Computing SAN JOSE, Calif., Aug. 30, 2022 /PRNewswire/ — MIPS, a leading developer of highly scalable RISC...
MIPS is thrilled to be part of Imperas’ Open Standard RISC-V Verification Interface (RVVI)
- July 13, 2022
July 11th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface)...
MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability
- May 26, 2022
Previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors SAN JOSE, Calif. – May 10, 2022 – MIPS,...
MIPS chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA compatible IP cores
- March 28, 2022
SILICON VALLEY, CA, USA – March 28, 2022. Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS...
MIPS selects Imperas Reference Models for RISC-V Processor Verification
- November 29, 2021
Oxford, United Kingdom – November 29th, 2021 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the...
Gaming Info Tech: MIPS Claims “Greatest-In-Class Efficiency” With New RISC-V eVocore CPUs
- May 12, 2022
MIPS Tech is now not engaged on their MIPS CPU instruction set structure however has been taking up RISC-V based mostly designs. At...