MIPS Takes Top Honors at Embedded World for eVocore P8700 Multiprocessor
- March 16, 2023
Company’s First RISC-V Product Paves Way for Future of Chip Development SAN JOSE, Calif., March 16, 2023 /PRNewswire/ — MIPS, a leading...
MIPS Leverages Siemens’ Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor
- May 30, 2023
New Platform to Accelerate Time-to-Market and Reduce Costs & Bottlenecks for SoC Developers SAN JOSE, Calif., May 30, 2023 /PRNewswire/ — MIPS,...
Imperas Collaborates with MIPS and Ashling to Accelerate RISC-V Application Software Development from SoC Concept to Deployment
- March 13, 2023
Oxford, United Kingdom – March 13th, 2023 – Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced with MIPS...
MIPS Named Embedded Award Nominee for eVocore P8700 Multiprocessor
- February 28, 2023
Prestigious Global Industry Accolades Honor Top Embedded Systems Innovations SAN JOSE, Calif., Feb. 28, 2023 — MIPS, a leading developer of highly scalable...
MIPS Announces Availability of its first RISC-V IP core – the eVocore P8700 Multiprocessor
- December 12, 2022
Industry’s Highest Performance, Most Scalable RISC-V IP Core Already Adopted for Next-Generation Automotive Applications San Jose, Calif., Dec. 12, 2022 — As the...
MIPS Partners With Mobileye to Accelerate Next Generation Autonomous Driving Technologies and Advanced Driver Assistance Systems
- December 12, 2022
Mobileye Adopts New MIPS eVocore RISC-V CPUs; RISC-V Architecture to Help Drive Future of Vehicle Safety San Jose, Calif., December 12, 2022- MIPS,...
MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors
- December 7, 2022
Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models, Verification...
We’re Getting Ready to Launch Something Big at RISC-V Summit 2022!
- December 6, 2022
RISC-V Summit has always been the ideal venue to unveil new innovations that drive higher performance and greater scalability for today’s complex applications....
Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V
- August 30, 2022
Architecture Will Accelerate Innovation in Open Computing SAN JOSE, Calif., Aug. 30, 2022 /PRNewswire/ — MIPS, a leading developer of highly scalable RISC...
MIPS is thrilled to be part of Imperas’ Open Standard RISC-V Verification Interface (RVVI)
- July 13, 2022
July 11th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface)...
MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability
- May 26, 2022
Previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors SAN JOSE, Calif. – May 10, 2022 – MIPS,...
MIPS chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA compatible IP cores
- March 28, 2022
SILICON VALLEY, CA, USA – March 28, 2022. Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS...
MIPS Expands RISC-V Ecosystem Support to Enable Early Software Development for Multi-threaded Cores
- April 4, 2024
MIPS Expands Global Footprint with New Design Center and Talent for Systems Architects and AI Compute
- March 20, 2024
RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA
- March 6, 2024
What’s the Difference Between Conventional Memory Protection and CHERI?
- March 6, 2024
MIPS Aims to Give Back Control, for AI-Centric Compute
- January 12, 2024
MIPS this week used CES 2024 to announce its new strategic focus and at the same time rebrand, under a mission to “give...
Another Major Player Shakes Up the RISC-V Arena
- January 11, 2024
MIPS has been known for delivering low-power, high-performance embedded processor designs, but its MIPS architecture has been eclipsed by other RISC architectures like...
CES: MIPS CEO Sameer Wasson sees RISC-V as path to freedom
- January 11, 2024
Sameer Wasson is passionate about RISC-V architecture and recently became CEO of MIPS to show the world how important an architecture it is....
Why is MIPS Putting its Primary Focus on RISC-V?
- January 11, 2024
MIPS has been know for delivering low power, high performance embedded processor designs but its MIPS architecture has been eclipsed by other RISC...
Is MIPS Poised to Take the RISC-V World by Storm?
- January 11, 2024
Sometimes the world can be a funny old place. Take computer companies, for example. Some (like IBM) seem to have been around forever,...
China Is All In on a RISC-V Future
- January 8, 2024
The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The...
CES Is Back and AI Will Take Center Stage. Here’s What Else to Expect From Tech’s Biggest Show.
- January 8, 2024
This coming week, a ridiculous number of people will be in Las Vegas for the annual extravaganza that is CES. First held in...
Linux 6.7 release – Main changes, Arm, RISC-V, and MIPS architectures
- January 8, 2024
So we had a little bit more going on last week compared to the holiday week before that, but certainly not enough to...