MIPS Blog
Unlocking the Power of Edge AI Through Efficient Data Movement
- March 27, 2024
In today’s interconnected world, the advancement of Edge AI has revolutionized the way we process and analyze data. Edge AI brings intelligence closer...
MIPS Launches New Strategic Focus and ReBrand: The Freedom to Innovate Compute
- January 9, 2024
Today is an exciting day at MIPS as we launch a rebrand and strategic focus on giving our customers the Freedom to Innovate...
Whitepapers
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Auto Re-vectorization Whitepaper
The methodology was designed to systematically transform other vector/SIMD ISA (x86 AVX, ARM SVE/Neon, etc) intrinsic code into RISC-V Vector assembly and analyze its performance metrics. The procedure consists of first converting the input intrinsic code (other vector ISA) to LLVM Vector IR, then modifying the input ISA attributes to RISC-V Vector attributes, applying LLVM vector optimization passes (for a specific RISC-V Vector Processor) and finally lowering the optimized LLVM Vector IR to the target RISC-V Vector CPU assembly code.
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The Benefits of Hardware Multi-Threading
Increase Silicon Efficiency for Higher Data Processing with the Same Area and Power
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HyperFRAME Research
HyperFRAME Research delivers in depth research and insights across the global technology landscape, spanning everything from hyperscale public cloud to the mainframe and everything in between. HyperFRAME industry analysts have published their analysis of the MIPS Atlas portfolio and turnkey approach to Physical AI compute subsystems.
