The MIPS ARC processor portfolio offers two Memory Protection Unit (MPU) options, one for the ARC 600 family, the other for the ARC EM and ARC HS families.

A a complete set of tools, runtime software and libraries that provides everything needed to develop embedded vision applications on the ARC EV6x Processor family.

The MIPS ARC® MetaWare MX Development Toolkit is a complete suite of tools, SDKs, runtime software and libraries that provide everything needed to program the ARC NPX NPU IP and ARC VPX DSP processors.

MIPS MetaWare For Safety products have been certified as ASIL D certified, so customers require no additional tool qualification when using them according to the Safety Manual.

The tightly coupled microDMA option for ARC EM cores enables low latency, energy efficient DMA transfers.

MIPS provides a comprehensive software offering including safety manager library, software test library and functional safety C runtime library building blocks for safety-critical applications.

The ARC HS MMU enables the core to run sophisticated embedded operating systems that support both Symmetric Multiprocessing (SMP) and virtual memory providing hardware support and acceleration for address translation and protection.

The MIPS ARC® processor portfolio offers two Memory Protection Unit (MPU) options. One is available for the ARC 600 family, the other for the ARC EM family. The ARC MPU is a separately licensable configuration option.

Learn about MIPS ARC NPX6FS Neural Processors for Functional Safety, supporting ISO 26262 for ADAS and autonomous vehicles.

ARC NPX6 and NPX6FS NPU IP meet the requirements of emerging AI applications such as advanced driver assistance systems (ADAS), surveillance, digital TVs and cameras.