MIPS ARC-V RPX-100 Processor IP features a dual-issue, 64-bit superscalar architecture for use in high performance applications where performance efficiency is required. The cores offer outstanding performance delivering with minimal power consumption.

The MIPS ARC-V RTX-100 series processors feature a dual-issue, 32-bit superscalar architecture for use in applications where real-time performance is required. The cores offer outstanding performance with a small area footprint and low power consumption.

MIPS ASIP Designer accelerates design and verification of application-specific instruction-set processors (ASIP) and programmable accelerators.

MIPS’ ASIP Designer offers an efficient way to design, implement, program and verify your application-specific instruction set processor (ASIP).

MIPS ARC XY Advanced DSP is designed to accelerate data processing, eliminate separate DSP and logic blocks and address complex computation problems in SoCs.

The MIPS ARC® Sensor IP Subsystem provides designers with a complete and pre-verified solution that meets the requirements of a broad range of applications such as such as intelligent sensors, sensor fusion, and sensor hub increasingly prevalent in automotive, mobile, industrial and smart energy markets.

The MIPS ARC® nSIM Instruction Set Simulator provides an instruction accurate processor model to take enable early start software development.

MIPS ARC® xCAM provides 100% cycle-accurate models of ARC IP, providing performance analysis of software before finalizing hardware design.

The MIPS ARC® Data Fusion IP Subsystem is a complete, pre-verified, hardware and software solution optimized for a wide range of ultra-low power IoT applications.