July 11th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface) for RISC-V processor verification with virtual peripherals to support asynchronous events and system level interrupts. Plus, the growing adoption of RVVI by many leading development teams that are driving the design innovations
With its transition to RISC-V, MIPS is targeting the high-performance segment of the processor market, leveraging its differentiation in real-time features
MIPS pivots to RISC-V, targets high performance processing Read More »
MIPS is showing the first results of its pivot to the RISC-V architecture following the collapse of Wave Computing.
EENews Europe: MIPS Previews its Pivot to RISC-V Read More »
MIPS, a developer of RISC processor IP, is entering into the RISC-V market and has offered previews of its first products in its eVocore product line-up.
New Electronics: MIPS enters RISC-V market with eVocore product line-up Read More »
MIPS is dead, right? Well, there’s now very little done on the architecture itself, MIPS (the company) has decided to switch to RISC-V architecture, and unveiled the eVocore product lineup currently comprised of the eVocore P8700 and I8500 multiprocessor IP cores.
CNX Software: MIPS unveils RISC-V eVocore P8700 and I8500 multiprocessor IP cores Read More »
SAN JOSE, Calif., May 10, 2022 — MIPS, a leading developer of highly scalable RISC processor IP, announces its entrance to the RISC-V market, previewing the first products in its eVocore product lineup. The new eVocore P8700 and I8500 multiprocessor IP cores are the first MIPS products based on the RISC-V open instruction set architecture
HPC Wire: MIPS Pivots to RISC-V with Performance and Scalability Read More »
MIPS Tech is no longer working on their MIPS CPU instruction set architecture but has been taking on RISC-V based designs. Today the company made the bold announcement for their new eVocore P8700 and I8500 multiprocessor IP cores that they offer “Best-In-Class Performance and Scalability.”
Phoronix: MIPS Claims “Best-In-Class Performance” with New RISC-V eVocore CPUs Read More »
MIPS Tech is now not engaged on their MIPS CPU instruction set structure however has been taking up RISC-V based mostly designs. At this time the corporate made the daring announcement for his or her new eVocore P8700 and I8500 multiprocessor IP cores that they provide “Greatest-In-Class Efficiency and Scalability.”
Previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors SAN JOSE, Calif. – May 10, 2022 – MIPS, a leading developer of highly scalable RISC processor IP, announces its entrance to the RISC-V market, previewing the first products in its eVocore™ product lineup. The new eVocore P8700 and I8500 multiprocessor
MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability Read More »
SILICON VALLEY, CA, USA – March 28, 2022. Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS RISC-V ISA based IP cores. RiscFree™ is Ashling’s Integrated Development Environment (IDE) including a compiler and debugger for RISC-V based development, and it now has support for MIPS RISC-V ISA based IP cores,
MIPS chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA compatible IP cores Read More »
