MIPS Atlas I8500
Award Winning I8500: Orchestrating Data Movement for Physical AI
I8500 Series Applications
Datacenter
- Ultra-low latency packet processing and coherent accelerator management to offload main CPUs, reduce power and bandwidth requirements
- High throughput multithreaded architecture scalable to many clusters for up to 1536 data streams
Physical AI
- Secure and deterministic data management for real-time applications
- Local protocol management and processing with accelerator management for edge compute
Aerospace & Defense
- Deterministic real-time processing ensures real-time control in mission-critical systems under extreme conditions
- Secure memory and cache designs and hypervisor support to safeguard sensitive data
Communications
- High throughput, packet processing with low-latency accelerator offload
- Secure data management and quality of service for reliable network operation
Efficient data management for physical AI applications
MIPS I8500™ Series: High-throughput, deterministic processor enabling low-latency offload to coherent accelerators for workloads that need real-time control and secure processing.
The I8500 is a very robust and scalable processor that employs 4-way simultaneous multithreading to achieve industry-leading performance per area. It is ideal for data movement and packet processing applications and can be configured in designs ranging from a single core to hundreds of cores in a coherent multi-cluster design.
I8500 Multiprocessing System Datasheet
The MIPS I8500™ Multi-Processing System (MPS) builds on a long history of high performance multi-threaded and multiprocessor IP products. The I8500 supports the RVB23 profile of the RISC-V base ISA and mandatory extensions, plus a number of optional RISC-V extensions. It also includes further enhancements for a variety of functions and operations through MIPS-Defined Instructions (MDIs), a set of custom instructions provided as an extension from MIPS to the standard RISC-V ISA and related features.
MIPS Atlas I8500
The MIPS Atlas I8500 processor provides industry-leading throughput and real-time processing for dataplane,
embedded edge and communications markets.
MIPS I8500™ Processor Orchestrates Data Movement for the AI Era
MIPS I8500 delivers deterministic, secure data orchestration for Physical AI with 3rd generation four-thread-per-core processor built using open RISC-V ISA.
Introducing MIPS Sense data movement engines
Autonomous platforms sense the world around them with a variety of inputs, from radar, lidar, and cameras, to gyroscopes, accelerometers, and atmospheric sensors. These sensors are rapidly increasing in fidelity with more resolution, color depth, accuracy, and increased sampling periods generating exponentially more data. Fusing this data together, establishing priorities and the right data formats, and moving it to the right compute elements is key to enabling accurate, fast decision making in edge platforms. Data orchestration systems from MIPS enable low-latency movement for a variety of data intensive applications
MIPS I8500™ and GlobalFoundries: Boosting AI Data Movement Efficiency Integrating Data and Control Planes for Physical AI Workloads
Artificial intelligence is moving from data centers into the physical world — from cloud-hosted chatbots to in-the-field robots: autonomous machines, industrial controllers, and connected infrastructure. These Physical AI systems must sense, think, act, and communicate (STAC) in real time. Yet most current architectures remain divided between control-plane CPUs and data-plane accelerators, introducing latency, power inefficiency, and software complexity.
Getting Started with I8500 Core Model
- Install Visual Studio
Install Visual Studio Code - Install Atlas Explorer extension
Visual Studio Marketplace - Work with your MIPS account team
Partner Portal Access
Complete user agreement
Obtain API Key - Download I8500 virtual platform package
Including user guides and support videos - Build your workload
Run model and view results
Efficient Throughput
- Superscalar 3-Wide, 9-stage, in-order pipeline
- Efficient data-centric processing
- 4-Way Simultaneous multi-threading (SMT), with no switching overhead
- Low latency and deterministic data access
- RISC-V Compliant ISA
- RVB23
- CMO Extension, Hardware virtualization (H Extension)
- MIPS Defined Instructions (MDI)—Cache and TLB management, Performance enhancements and DVM (Distributed Virtual Memory) support
- Optional up to 1MB Data and Instruction ScratchPad RAMs (DSPRAM, ISPRAM) for real-time, low-latency applications
Coherence Manager
- Support for up to 8 coherent initiators comprising of either MIPS RISC-V Processors or 3rd party accelerators
- Cluster Level-2 Cache L2$ up to 2MB
- Hardware pre-fetch
- System interface(s):
- ACE or AXI: Configurable 128/256/512-bit system bus
- Optional: Non-coherent periphery busses (up to 4 ports)
