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Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V

Architecture Will Accelerate Innovation in Open Computing SAN JOSE, Calif., Aug. 30, 2022 /PRNewswire/ — MIPS, a leading developer of highly scalable RISC...

MIPS is thrilled to be part of Imperas’ Open Standard RISC-V Verification Interface (RVVI)

July 11th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface)...

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability

Previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors SAN JOSE, Calif. – May 10, 2022 – MIPS,...

MIPS chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA compatible IP cores

SILICON VALLEY, CA, USA – March 28, 2022. Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS...

MIPS selects Imperas Reference Models for RISC-V Processor Verification

Oxford, United Kingdom – November 29th, 2021 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the...

Restructured Wave Computing/MIPS Business Moves ahead as MIPS

SANTA CLARA, Calif., March 1, 2021 /PRNewswire/ — Wave Computing, Inc. (“Wave”) and its subsidiaries including MIPS Tech, the processor technology company focused...

MIPS at 40

MIPS is celebrating its 40th anniversary as a compute IP company this year. Known for a RISC instruction set, the company has risen...

Not All RISC-V IP is the Same

MIPS CEO Sameer Wasson discusses the company’s approach to RISC-V and how its P8700 RISC-V cores stack up against the competition....

Multicore RISC-V Designs for Smart Automotive Apps

A cluster of six MIPS P8700 RISC-V cores can be replicated up to 64 times to support 768 execution threads....

AI-Enabled RISC-V Cores Target ASIL B Automotive Apps

The MIPS P8700 RISC-V core, which implements a RISC-V ISA, aims at ASIL B and ISO 26262 functional safety....

MIPS releases RISC-V CPU for autonomous vehicles

MIPS released its P8700 CPU based on the RISC-V computing architecture to target driver assistance and autonomous vehicle applications....

Addressing AI While Keeping the MIPSiness In MIPS

MIPS, now targeting AI applications for its application-specific data movement cores, is evolving with a careful eye on its strengths....

Sameer Wasson: Have a Steady Hand, Don’t be Distracted

In this episode of Silicon Grapevine, we talk to MIPS CEO Sameer Wasson about the experience of going from an intern doing FPGA...

The New MIPS – Solving Compute Where It Happens

Timing, opportunity and geographic location matter in life – when we decide to do important things and where we decide to live and...

Embedded Quest at Embedded World

In our quest for "useful" embedded systems, the Ojo-Yoshida Report roamed the show floor at Embedded World, cornering vendors and asking two questions:...

MIPS Adds 3 Managers from NVIDIA, Google and SiFive

MIPS, a developer of efficient and configurable IP compute cores, today announced the addition of three technology and semiconductor industry professionals dedicated to...

MIPS Expands RISC-V Ecosystem Support to to Enable Early Software Development for Multi-threaded Cores

MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc. to...

MIPS RISC-V ecosystem supports early software development

MIPS has announced that it has expanded its collaboration with Synopsys to accelerate ecosystem enablement of MIPS RISC-V IP and their customer’s ability...

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