newmips, Author at MIPS

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability

Previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors SAN JOSE, Calif. – May 10, 2022 – MIPS, a leading developer of highly scalable RISC processor IP, announces its entrance to the RISC-V market, previewing the first products in its eVocore™ product lineup. The new eVocore P8700 and I8500 multiprocessor […]

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MIPS chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA compatible IP cores

Press Releases / newmips

SILICON VALLEY, CA, USA – March 28, 2022. Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS RISC-V ISA based IP cores. RiscFree™ is Ashling’s Integrated Development Environment (IDE) including a compiler and debugger for RISC-V based development, and it now has support for MIPS RISC-V ISA based IP cores,

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MIPS selects Imperas Reference Models for RISC-V Processor Verification

Press Releases / newmips

Oxford, United Kingdom – November 29th, 2021 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the processor technology company focused on the commercialization of RISC-based processor architectures and IP cores, the continuation and extension to the long-standing relationship with simulation and verification support for RISC-V. Since 2010, MIPS has partnered

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Restructured Wave Computing/MIPS Business Moves ahead as MIPS

Press Releases / newmips

SANTA CLARA, Calif., March 1, 2021 /PRNewswire/ — Wave Computing, Inc. (“Wave”) and its subsidiaries including MIPS Tech, the processor technology company focused on the commercialization of RISC-based processor architectures and IP cores, today emerged from Chapter 11 bankruptcy protection. Going forward, the restructured business (“the Company”) will be known as MIPS, reflecting the Company’s strategic focus on

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Author name: newmips

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability

MIPS chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA compatible IP cores

MIPS selects Imperas Reference Models for RISC-V Processor Verification

Restructured Wave Computing/MIPS Business Moves ahead as MIPS