The MIPS ARC 605 is a low-power, small 32-bit configurable processor core IP processor ideal for a wide range of embedded control and computing functions within SoCs.

Fully configurable ARC processor based hardware and software subsystems reduce SoC design time, lower risk, and accelerate time to market.

32-/64-bit ARC HS processors are optimized for GHz+ operating speeds with minimum area and power consumption for very-high performance embedded applications.

MIPS ARC® SEM Family of performance-efficient, ultra-low power, compact security processors enables designers to integrate security into their SoCs.

The ARC LC3 codec algorithm is a low complexity communications codec within the Bluetooth standard, to deliver voice and audio streaming.

The MIPS ARC® HS Development Kits are ready-to-use platforms for rapid software development on the ARC HS3x and HS4x/4xD processor families.

The ARC HS L2 cache option is user configurable from 128KB to 8 MB and can be used with a single-core or multi-core implementation with all CPUs in a multicore cluster sharing the same L2 cache.

Ultra-compact ARC EM processors offer excellent code density, small size, and low power consumption for constrained embedded and deeply embedded applications.

Complete, configurable, extendible and high-performance processors that can easily be incorporated into SoC designs to enable high-quality audio applications.

A high-quality decoder that decodes up to 7.1 channel audio streams according to the AAC LC profiles of the ISO/IEC 14496-3 standard.