Extend Functionality with ARC Licensable Options
MIPS offers a portfolio of separately licensable options that enable MIPS ARC® processors to be optimized for a specific application or to add more processing capabilities. ARC processors are supported by a range of licensable options including floating point, security, automotive safety, memory protection, mathematical functions, debug and system integration, enabling designers to meet the unique requirements of their application.
| ARC EM | ARC SEM | ARC HS | ARC VPX | ARC EV | |
| Floating Point Unit (FPU) | ✓ | ✓ | ✓ | ✓ | ✓ |
| Memory Protection Unit (MPU) | ✓ | ✓ | |||
| Real-Time Trace (RTT) | ✓ | ✓ | ✓ | ✓ | |
| uDMA | ✓ | ✓ | |||
| Overlay Management Unit | ✓ | ||||
| Performance Option | ✓ | ||||
| Enhanced Security Package | ✓ | ||||
| CryptoPack | ✓ | ✓ | |||
| ARConnect | ✓ | ||||
| DNN Engine | ✓ |
PPA Efficiency
ARC processors are optimized to deliver the best PPA efficiency in the industry for embedded SoCs.
- Harvard architecture for higher performance through simultaneous instruction and data memory access
- High-speed pipeline designed for maximum power efficiency
- 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density
Configurability
ARC processors are highly configurable, allowing designers to optimize the performance, power, and area of each processor instance on their SoC.
- Add or omit hardware features to optimize the core for your target application – no wasted gates
- The ARChitect wizard enables drag-and-drop configuration of the core
Extensibility
ARC Processor EXtension (APEX) technology enables users to customize their processor implementation.
- Add user-defined instructions to accelerate software execution and reduce code size, reducing energy consumption and memory requirements
- Tightly couple memories and peripherals to the processors to eliminate the need for additional bus infrastructure, reducing area and latency and increasing system-level performance