With the vast amount of personal data stored in the cloud and transferred between smart devices, it is increasingly important to have effective security measures in place to avoid the threat of data breaches and malicious attacks.
Enhanced Security Package Option for ARC EM Cores
The Enhanced Security Package option available for MIPS ARC® EM Processors enables designers to create a tamper-resistant, secure environment that protects their systems and software from vulnerabilities using a single ultra-low power processor.
The option includes SecureShield™ technology to enable development of a trusted execution environment, reducing the area and power that an additional security core and associated memories would require. SecureShield technology protects critical processor registers like stack and instruction pointer registers as well as secure bus accesses, and includes a secure memory protection unit (MPU) to protect traditional instruction and data memory. The secure MPU has up to 16 configurable memory regions with the option for per region scrambling and encryption.
Designers can also add user-defined instructions and co-processors through the ARC Processor EXtension (APEX) technology and restrict their operations to a secure mode, enabling IP protection throughout the value chain.
Enhanced Security Package Option for ARC HS Cores
As with the ARC EM processors, designers can add user-defined instructions and co-processors through the ARC Processor EXtension (APEX) technology for cryptographic or encryption purposes.
ARC CryptoPack Option for EM Cores
The MIPS ARC® CryptoPack option provides the ability to speed up software encryption implementations by adding custom instructions and registers to the ARC EM processors using the ARC Processor EXtension (APEX) interface. Supported software algorithms include Advanced Encryption Standard (AES), Triple Data Encryption Standard (3DES ), Elliptic Curve Cryptography (ECC), Secure Hash Algorithm with 32-bit words (SHA-256) and Rivest-Shamir-Adleman (RSA) encryption.
Secure Your IoT Device with Ultra-Low Power ARC Processors
Learn how DesignWare ARC Processors help secure your IoT design without an extra security core, keeping area and power consumption to a minimum. Please download the white paper “Securing the Internet of Things: An Architect’s Guide to Securing IoT Devices Using Hardware Rooted Processor Security”
Highlights & Key Features
- Enhanced Security Package
- Includes SecureShield technology to enable a trusted execution environment
- Secure MPU with up to 16 configurable regions and per region scrambling/encryption capability
- In-line instruction and data encryption and address scrambling to protect algorithms from reverse engineering or IP theft
- Data and instruction path integrity checking to prevent fault injection attacks
- Integrated watchdog timer detects system failures that can result from tampering and enables counter measures
- Ability to add secure custom instructions or co-processors in a trusted mode boosts performance and reduces power
- CryptoPack
- Easy to add option for EM Family of processors
- Area-optimized and performance-optimized versions to scale to system goals
- Up to 7x or more speedup to perform cryptographic functions
- Supported cryptographic software algorithms
- AES
- 3DES
- ECC
- SHA-256
- RSA
- Enhanced Security Package for MIPS ARC HS Processor Family Datasheet
- Intrinsic-ID Physically Unclonable Function (PUF) Solution for MIPS ARC EM Processors
- Enhanced Security Package for MIPS ARC EM Processor Family Datasheet
- MIPS ARC CryptoPack: Extensions for Cryptographic Software Acceleration Datasheet
Product Details
| Description | CryptoPack is a set of APEX based instructions to accelerate software cryptography algorithms on ARC EM processors |
| Name | dwc_arc_em_cryptopack |
| Version | 1.10a |
| ECCN | 5D002.b2/ENC |
| STARs | Open and/or Closed STARs |
| myDesignWare | Subscribe for Notifications |
| Product Type | DesignWare Cores |
| Documentation | Show Documents Hide Documents White PaperRight-Sizing Your Cryptographic Processing Solution ( PDF ) |
| Toolsets | Qualified Toolsets |
| Download | dwc_arc_em_cryptopack |
| Product Code | B206-0 |
| Description | Enhanced Security Package option for ARC EM Processors |
| Name | dwc_arc_em_esp |
| Version | 5.70b |
| ECCN | 3E991/NLR |
| STARs | Open and/or Closed STARs |
| myDesignWare | Subscribe for Notifications |
| Product Type | DesignWare Cores |
| Documentation | Show Documents Hide Documents DatasheetEnhanced Security Package for MIPS ARC EM Processor Family Datasheet ( PDF ) User GuideARC EM22FS Implementation and Integration Guide (5.70a) ( HTML ) ARC EM22FS Implementation and Integration Guide (5.70b) ( PDF ) White PaperConfigurable and Extensible 32-Bit RISC Processors for Next-Generation SSDs ( PDF ) Right-Sizing Your Cryptographic Processing Solution ( PDF ) White Paper: Securing the Internet of Things Using Hardware Rooted Processor Security - An Architect's Guide ( PDF ) |
| Toolsets | Qualified Toolsets |
| Download | dwc_arc_em_esp |
| Product Code | B754-0 |
| Description | Enhanced Security Package option for ARC HS cores |
| Name | dwc_arc_hs_esp_option |
| Version | 4.10a |
| ECCN | 3E991/NLR |
| STARs | Open and/or Closed STARs |
| myDesignWare | Subscribe for Notifications |
| Product Type | DesignWare Cores |
| Documentation | Show Documents Hide Documents DatabookARC HS4x Series Databook (4.10a) ( PDF ) ARC HS4x Series Databook (Beta) ( PDF ) ARC Trace Databook (4.10a) ( PDF ) ARC Trace Databook (Beta) ( PDF ) HAPS Reference Design Flow Databook (4.10a) ( PDF ) Implementation GuideARC HS4x Implementation and Integration Guide (4.10a) ( PDF ) ARC HS4x Implementation and Integration Guide (Beta) ( PDF ) Reference ManualARCv2 FPGA Synthesis Flow (4.10a) ( PDF ) ARCv2 ISA Programmer's Reference Manual for ARC HS4x Processors (4.10a) ( PDF ) User GuideARC MIPS ASIC Reference Design Flow User's Guide (4.10a) ( PDF ) |
| Toolsets | Qualified Toolsets |
| Download | dwc_arc_hs_esp_option |
| Product Code | E038-0 |