Overview
The MIPS ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the highly-efficient ARCv2 instruction set architecture (ISA) and pipeline that deliver a high degree of performance efficiency and code density with minimal power and area for embedded applications. The ARC HS3x processors can be configured as dual core or quad core for maximum performance.
The HS34 processor is optimized for use in high-end embedded applications where real-time, deterministic response is desired, such as SSD controllers, baseband control, digital TV, home networking, automotive systems and smart appliances.
The HS36 processor has all the features of the HS34 and adds support for up to 64KB of instruction and data cache. The HS36 processors is ideally suited for high-performance embedded applications such as SSD controllers, networking, medical, and industrial & automotive systems.
The ARC HS38 processors is optimized for use in high-performance embedded applications running Linux. The processor has a full-featured Memory Management Unit (MMU) supporting a 40-bit physical address space and page sizes up to 16 megabytes (MBs), giving designers the ability to directly address a terabyte of memory with faster data access and higher system performance. It also supports SMP Linux, full Level 1 cache coherency and up to 8 MB of Level 2 cache.
To minimize system-level latency and increase overall system performance, the HS3x processors all support close coupled memories and direct mapping of peripherals, providing single-cycle access to other IP and memory blocks on the SoC. Native ARM® AMBA® AXI™ and AHB™ standard interfaces are configurable for 32-bit or 64-bit transactions to optimize throughput.
The ARC HS Family is supported by a robust ecosystem of software and hardware development tools, including the MetaWare Development Kit, a complete solution for developing, debugging, and optimizing embedded software on ARC processors, the MQX real-time operating system (RTOS) and a portfolio of third-party tools, operating systems and middleware from leading industry vendors through the ARC Access Program.
Highlights
- Achieves up to 3232 DMIPS and 6681 CoreMarks* at 1.61 GHz on 28HPM (single-core configuration, worst case silicon and conditions)
- Delivers 2.13 DMIPS/MHz, 4.15 CoreMarks/MHz* (per core)
- High-speed, 10-stage pipeline
- Up to 16MB instruction and data close coupled memory (CCM)
- Single-, dual- or quad-core configurations
- 64-bit loads and stores
- 64-bit multiply, multiply-accumulate
- Radix-4 hardware divider
- Optional IEEE 754-compliant floating point unit - single or double precision
- Selectable ECC protection for all memories in the processor
- Low-latency port for fast access to peripherals or memory
- Up to 240 interrupts, with up to 16 configurable preemption levels
- Native ARM® AMBA® AXI™, AHB™ interfaces
- JTAG and Compact JTAG (cJTAG) debug interface
- Optional real-time trace
- MMU with 40-bit physical address space (HS38, separately licensable for HS36)
- 4KB to 64KB instruction and data cache (HS36 and HS38 only)
- Dual- and quad-core version with support for SMP Linux with L1 coherency (HS36 and HS38)
- Up to 8MB L2 cache (HS38, separately licensable for HS36)*CoreMark: 1.0 : 4.15 / MetaWare C/C++ Compiler N-2017.12 - O -Hmerge -Hall_sdata -Hccm -Haggressive_unroll -Hloop_sms -Hinlsize=800 -Hunroll=400 -mllvm -zdloops -Hpipeline -Hmax_predicate=1 -Xunaligned / xCAM integrated model simulated @ 1 MHz
- Memory Management Unit (MMU)
- L2 Cache
- Floating Point
- Memory Protection
- Mathematical Functions
- Debug
- Cluster DMA
Licensable Options
- Memory Management Unit (MMU)
- L2 Cache
- Floating Point
- Memory Protection
- Mathematical Functions
- Debug
- Cluster DMA
Product Details
Products
| ARC HS34 32-bit processor core, ARC V2 ISA, for embedded applications | STARs | Subscribe |
| ARC HS34x2 dual-core version of HS34 for embedded real-time applications | STARs | Subscribe |
| ARC HS34x4 quad-core version of HS34 for real-time embedded applications | STARs | Subscribe |
| ARC HS36 32-bit processor core, ARC V2 ISA, for embedded applications | STARs | Subscribe |
| ARC HS36x2 dual-core version of HS36 with I and D cache for high-performance embedded applications | STARs | Subscribe |
| ARC HS36x4 quad-core version of HS36 with I and D cache for high-performance embedded applications | STARs | Subscribe |
| ARC HS38 32-bit processor with MMU, ARCv2 ISA, for embedded Linux applications | STARs | Subscribe |
| ARC HS38x2 dual-core 32-bit processor with MMU, ARCv2 ISA, for embedded Linux applications | STARs | Subscribe |
| ARC HS38x4 quad-core 32-bit processor with MMU, ARCv2 ISA, for embedded Linux applications | STARs | Subscribe |
| L2 cache option for multicore versions of ARC HS36 and HS38 processors | STARs | Subscribe |
| The FastMath Pack is a math processing accelerator for the ARC HS family | STARs | Subscribe |
Downloads & Documentation
| Description | ARC HS34 32-bit processor core, ARC V2 ISA, for embedded applications |
| Name | dwc_arc_hs34_core |
| Version | 4.10a |
| ECCN | 3E991/NLR |
| STARs | Open and/or Closed STARs |
| myDesignWare | Subscribe for Notifications |
| Product Type | DesignWare Cores |
| Documentation |
Application Notes ARC Processors Not Susceptible to Meltdown and Spectre Vulnerabilities ( PDF )
Manual RAM Replacement in ARC Cores ( PDF )
Databook ARC HS APEX Databook (4.10a) ( PDF )
ARC HS3x Series Databook (Beta) ( PDF )
ARC Trace Databook (4.10a) ( PDF )
ARC Trace Databook (Beta) ( PDF )
HAPS Reference Design Flow Databook (4.10a) ( PDF )
Datasheet MIPS ARC HS3x Processors Datasheet ( PDF )
Reference Manual ARCv2 FPGA Synthesis Flow (4.10a) ( PDF )
ARCv2 ISA Programmer's Reference Manual for ARC HS3x (4.10a) ( PDF )
ARCv2 ISA Programmer's Reference Manual for ARC HS3x and 4x Processors (Public Edition) ( PDF )
ARCv2 ISA Programmer's Reference Manual for ARC HS4x (Beta) ( PDF )
ARCv2 ISA Programmer's Reference Manual for ARC HS4xFS (Beta) ( PDF )
User Guide ARC HS3x Implementation and Integration Guide (4.10a) ( PDF )
ARC HS3x Series Databook (4.10a) ( PDF )
ARC MIPS ASIC Reference Design Flow User's Guide (4.10a) ( PDF )
|
| Toolsets | Qualified Toolsets |
| Download | dwc_arc_hs34_core |
| Product Code | 7850-0 |
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