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MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors

Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models,

We’re Getting Ready to Launch Something Big at RISC-V Summit 2022!

RISC-V Summit has always been the ideal venue to unveil new innovations that drive higher performance and greater scalability for today’s complex

Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V

Architecture Will Accelerate Innovation in Open Computing SAN JOSE, Calif., Aug. 30, 2022 /PRNewswire/ — MIPS, a leading developer of highly scalable

MIPS is thrilled to be part of Imperas’ Open Standard RISC-V Verification Interface (RVVI)

July 11th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification

MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability

Previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors SAN JOSE, Calif. – May 10, 2022 –

MIPS chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA compatible IP cores

SILICON VALLEY, CA, USA – March 28, 2022. Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support

MIPS selects Imperas Reference Models for RISC-V Processor Verification

Oxford, United Kingdom – November 29th, 2021 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc.,

Restructured Wave Computing/MIPS Business Moves ahead as MIPS

SANTA CLARA, Calif., March 1, 2021 /PRNewswire/ — Wave Computing, Inc. (“Wave”) and its subsidiaries including MIPS Tech, the processor technology company

China Deploys Massive RISC-V Server in Commercial Cloud

If the U.S. government intends to curb China’s adoption of emerging RISC-V architecture to develop homegrown chips, it may be getting late.

Embedded Computing Design: MIPS Plans Expansion, Pulls New CEO from TI

The recent growth in RISC-V interest and adoption is hard to deny, and MIPS, a developer of high-performance RISC-V compute IP, is

MIPS taps Siemens FPGA for RISC-V CPU roll out

MIPS is using an FPGA platform from Siemens Digital Industries Software to accelerate software development for its eVocore P8700 RISC-V multiprocessor.

Electronic Engineering: MIPS Rolls Out Its First RISC-V Processor Core

Even though the company had telegraphed its big move, MIPS’s adoption of the RISC-V ISA for its future processor cores hit me

EE Times: RISC-V Summit 2022: All Your CPUs Belong to Us

MIPS announced that Mobileye adopted its eVocore P8700 for the next-generation EyeQ SoC for autonomous driving and advanced driver assistance systems (ADAS).

All About Circuits: “RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes

RISC-V is everywhere. RISC-V is redefining computing. And that’s not just for this quarter. This is for the next era of computing.

New Electronics: MIPS makes first RISC-V IP core available

MIPS, a developer of scalable RISC processor IP, has announced the availability of the eVocore P8700, said to be the industry’s highest

EE World Online: Scalable RISC-V multiprocessor IP promotes efficient SoC uses

MIPS has announced the availability of the eVocore P8700, the industry’s highest-performance, most scalable RISC-V multiprocessor IP. The P8700 has already been

Forbes: MIPS Joins The RISC-V Gang

Perhaps the biggest news at the RISC-V Summit came from MIPS. The story of MIPS is as full of twists, turns, and

Design & Reuse: RISC-V Sees Significant Growth and Technical Progress in 2022 with Billions of RISC-V Cores in Market

Members across the ecosystem have continued to innovate with cutting-edge RISC-V hardware and software solutions. MIPS announced the availability of its first

Tech Insights: MIPS Releases First RISC-V CPUs

MIPS has developed its first licensable CPUs implementing the RISC-V instruction set by repurposing older MIPS-compatible cores. The P8700 and I8500 outperform

MIPS pivots to RISC-V, targets high performance processing

With its transition to RISC-V, MIPS is targeting the high-performance segment of the processor market, leveraging its differentiation in real-time features

Unlocking the Power of Edge AI Through Efficient Data Movement

By Dave Bell, Senior Director of Product Management, MIPS In today’s interconnected world, the advancement of Edge AI has revolutionized the way

MIPS Launches New Strategic Focus and ReBrand: The Freedom to Innovate Compute

By Sameer Wasson, CEO Today is an exciting day at MIPS as we launch a rebrand and strategic focus on giving our

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