electronica 2026
November 10 – 13, 2026
Munich, Germany
Booth # C3 Semi Hall, #540.
Visit us at electronica 2026!
The electronics industry is undergoing a major transformation as AI moves from the cloud to vehicles, industrial, and intelligent edge devices, driving demand for more efficient, scalable, and software-defined computing platforms.
Visit the MIPS booth to meet with our experts and explore innovative approaches for accelerating AI deployment while achieving demanding performance, efficiency, and safety requirements.
Attend our sessions in the Embedded Developer Forum at the Future Tech Stage (Hall C6, stand number 501)
Sean Murphy, Senior Director of Product, 32-bit Platform
Thursday, Nov 12, 10:40am
Utilizing the RISC-V Architecture to Accelerate Real-Time Applications
Sam Grove, Head of Software and Tools
Thursday, Nov 12, 4:40pm
Tailoring Platforms for Agentic AI Workloads Using Advanced Virtual Platforms for RISC-V
Mayank Mangla, AI Product/Systems Architect
Friday, Nov 13, 1:00pm
No RISC, No Reward: Unlocking Extreme Efficiency in Physical AI with RISC-V
Session Abstracts
Sean Murphy — Utilizing the RISC-V Architecture to Accelerate Real-Time Applications
In this talk, Sean will present a novel approach for accelerating real-time motor control applications using a MIPS‑defined trigonometric math custom instruction extension on RISC‑V. One of the most widely used algorithms in motor control is Field Oriented Control (FOC). Within the FOC loop, the Park and Inverse Park transformations require repeated sine and cosine computations, which can be a significant performance bottleneck in software-based implementations. He will walk through a simple software implementation of the FOC loop and demonstrate the minimal code changes required to take advantage of custom trigonometric instructions. By offloading these operations to dedicated execution units integrated directly into the CPU pipeline, the solution delivers substantial performance improvements at the algorithm and system level while maintaining a software-friendly programming model. The talk will also discuss why tightly integrated custom execution units can provide better performance, power efficiency, and area utilization compared to traditional accelerators or heterogeneous compute approaches. Using RISC‑V custom instructions, software developers can access application-specific hardware acceleration with minimal complexity and without rewriting core algorithms. He will conclude by showing how accelerating motor control algorithms enables more precise, faster, lighter, and more efficient motors—benefiting applications in robotics, industrial automation, electric vehicles, and emerging real-time AI systems.
Sam Grove — Tailoring Platforms for Agentic AI Workloads Using Advanced Virtual Platforms for RISC-V
The traditional model of selecting a CPU from a datasheet and then beginning software development is outdated. Today, customers need to optimize software while being able to influence the hardware. The hardware/software co-design paradigm shift drives new requirements: system-level virtual platforms; standards-based extensible hardware; and open toolchains. This session will explore how virtual platforms for software development and workload optimization bridges the gap between hardware and software, enabling early architecture exploration for a variety of processor cores. Sam will explain how MIPS Atlas Explorer supports RISC-V designs that conform to standard Profiles while still allowing for application-specific extensions. He will showcase Atlas Explorer in action through demos targeting RISC-V core models and deploying to commercially available hardware. Attendees will also get a glimpse of how Atlas Explorer is being used by industry leaders to tailor systems around real workloads, reducing cost and increasing platform confidence ahead of silicon.
Mayank Mangla — No RISC, No Reward: Unlocking Extreme Efficiency in Physical AI with RISC-V
Deployment of neural networks at the edge is often constrained by the rigidity and integration cost of domain-specific accelerators. In this talk, Mayank will address the “efficiency wall”: when an accelerator optimized for one architecture (e.g., CNNs) runs another (e.g., transformers), TOPS don’t translate into throughput. Leveraging the extensible RISC-V ISA, he will present a holistic hardware-software co-design that enhances a standard RISC-V CPU with extensions optimized for CNN and vision transformer operations—avoiding a separate accelerator and its integration overhead. Custom instructions provide fine-grained data path control, cutting data movement and power consumption. He will share results showing greater energy efficiency in physical AI applications. Complementing the hardware, an ISA-aware software ecosystem streamlines moving models from PyTorch/TensorFlow to optimized implementations without manual kernel tuning, decoupling model definition from hardware specifics and enabling AI in use cases from IoT to automotive.