MIPS ARC 605 Processor Core

Designed for a broad range of embedded control functions within SoCs, the ARC 605 has a full 4GB addressing range and support for a Power Management Unit (PMU) that offers advanced power management capabilities. Based on a Harvard architecture the 605 features single-cycle close coupled memory (CCM) for both instruction and data spaces. The cacheless design provides fast and deterministic processor performance for embedded applications. User defined custom instruction extensions may be incorporated by the user to achieve even higher performance levels. The processor is implemented with the efficient ARCompact 16-/32-bit Instruction Set Architecture (ISA) that reduces code size by up to 40% compared to 32-bit-only instruction sets.

The MIPS ARC 605 is highly configurable and can be quickly and easily customized for a specific application, so designer can include only the features that they need minimizing power consumption and cost, while maximizing performance. The 605 is supported by a full suite of software and hardware development tools. The suite includes the MetaWare Development Kit that generates highly efficient code ideal for embedded applications, the ARC simulators including xCAM and nSIM, and the ARChitect configuration tool.