MIPS announced that Mobileye adopted its eVocore P8700 for the next-generation EyeQ SoC for autonomous driving and advanced driver assistance systems (ADAS).
EE Times: RISC-V Summit 2022: All Your CPUs Belong to Us Read More »
RISC-V is everywhere. RISC-V is redefining computing. And that’s not just for this quarter. This is for the next era of computing.
All About Circuits: “RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes Read More »
MIPS, a developer of scalable RISC processor IP, has announced the availability of the eVocore P8700, said to be the industry’s highest performance, most scalable RISC-V multiprocessor IP.
New Electronics: MIPS makes first RISC-V IP core available Read More »
MIPS has announced the availability of the eVocore P8700, the industry’s highest-performance, most scalable RISC-V multiprocessor IP. The P8700 has already been licensed for applications including automotive driver assistance systems (ADAS) and autonomous driving.
EE World Online: Scalable RISC-V multiprocessor IP promotes efficient SoC uses Read More »
Perhaps the biggest news at the RISC-V Summit came from MIPS. The story of MIPS is as full of twists, turns, and surprises as any you get in Silicon Valley.
Forbes: MIPS Joins The RISC-V Gang Read More »
Members across the ecosystem have continued to innovate with cutting-edge RISC-V hardware and software solutions. MIPS announced the availability of its first RISC-V IP core, the high performance and scalable eVocore P8700 multiprocessor. MIPS also partnered with Mobileye to accelerate next generation autonomous driving technologies and advanced driver assistance systems with MIPS’ eVocore P8700 RISC-V
MIPS has developed its first licensable CPUs implementing the RISC-V instruction set by repurposing older MIPS-compatible cores. The P8700 and I8500 outperform most other RISC-V designs.
Tech Insights: MIPS Releases First RISC-V CPUs Read More »
Industry’s Highest Performance, Most Scalable RISC-V IP Core Already Adopted for Next-Generation Automotive Applications San Jose, Calif., Dec. 12, 2022 — As the shift toward RISC-V accelerates across industries, the open standard instruction set architecture (ISA) is ushering a new wave of innovation and collaboration. In an effort to help fuel this trend, MIPS, a
Mobileye Adopts New MIPS eVocore RISC-V CPUs; RISC-V Architecture to Help Drive Future of Vehicle Safety San Jose, Calif., December 12, 2022- MIPS, a leading developer of highly scalable RISC processor IP, announced it is continuing its partnership with Mobileye, in accelerating innovation in autonomous driving technologies and advanced driver-assistance systems (ADAS). As part of
Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models, Verification IP, and test suites Oxford, United Kingdom, December 7th, 2022 — Imperas Software Ltd., the leader in RISC-V simulation solutions, announced today that MIPS, a leading developer of highly scalable RISC processor
