Chip designer MIPS has picked up two former execs from SiFive in a bid to boost its RISC-V development efforts. MIPS, the company that created the processor architecture of the same name, is now looking to the RISC-V open instruction set architecture for new products under the eVocore name. The eVocore P8700 has been shipping […]
MIPS snags top SiFive brains to amp up RISC-V business Read More »
MIPS, a leading developer of high- performance RISC-V compute IP, today announced the addition of two semiconductor industry veterans to its leadership team. Drew Barbier joins the company as VP of Products and Brad Burgess has been named Chief Architect. Both executives join the MIPS Executive Leadership team.
MIPS Welcomes New Executives as Part of Company’s Growth and Expansion Read More »
In a strategic move poised to invigorate the RISC architecture processors domain, MIPS Inc., a groundbreaking company in the sector, has announced the appointment of two industry stalwarts to its leadership team. Drew Barbier and Brad Burgess, both notable figures from SiFive Inc., a RISC-V pioneer, have now joined the ranks of MIPS. Barbier has
MIPS Inc. Boosts Leadership Team, Eyes RISC-V Market Expansion Read More »
Former SiFive Leaders to Help Drive IP Innovation and Market Penetration SAN JOSE, CA – January 03, 2024 – MIPS, a leading developer of high- performance RISC-V compute IP, today announced the addition of two semiconductor industry veterans to its leadership team. Drew Barbier joins the company as VP of Products and Brad Burgess has
MIPS Welcomes New Executives as Part of Company’s Growth and Expansion Read More »
MIPS, a storied CPU IP core company with a tortuous business/management history, is writing a new chapter under the watch of new CEO Sameer Wasson, formerly an executive at Texas Instruments. Can he lift MIPS from oblivion to relevance and solid growth? Wasson’s first order of business is to explain to the world who MIPS
Sameer Wasson’s Vision for MIPS/RISC-V Read More »
If the U.S. government intends to curb China’s adoption of emerging RISC-V architecture to develop homegrown chips, it may be getting late. Last month, China’s Shandong University deployed a server cluster with RISC-V CPUs. The system has a total of 3,072 cores, with 48 nodes of 64-bit RISC-V CPUs.
China Deploys Massive RISC-V Server in Commercial Cloud Read More »
Company’s First RISC-V Product Paves Way for Future of Chip Development SAN JOSE, Calif., March 16, 2023 /PRNewswire/ — MIPS, a leading developer of highly scalable RISC processor IP, has been named winner of the SoC/IP/IC Design category at this year’s embedded world International conference in Nuremberg, Germany. The annual embedded award honors outstanding
MIPS Takes Top Honors at Embedded World for eVocore P8700 Multiprocessor Read More »
The recent growth in RISC-V interest and adoption is hard to deny, and MIPS, a developer of high-performance RISC-V compute IP, is looking to grow right along with the rising tide.
Embedded Computing Design: MIPS Plans Expansion, Pulls New CEO from TI Read More »
MIPS is using an FPGA platform from Siemens Digital Industries Software to accelerate software development for its eVocore P8700 RISC-V multiprocessor.
MIPS taps Siemens FPGA for RISC-V CPU roll out Read More »
New Platform to Accelerate Time-to-Market and Reduce Costs & Bottlenecks for SoC Developers SAN JOSE, Calif., May 30, 2023 /PRNewswire/ — MIPS, a leading developer of highly scalable RISC processor IP, has collaborated with Siemens Digital Industries Software, a global electronic design automation leader, to speed time-to-market and accelerate software development for customers of
