Join us for this half-day virtual seminar to learn more about the power of ASIPs and ASIP Designer
Friday, September 25, 1:00pm – 5:00pm JST
Application-specific instruction set processors (ASIPs) have established themselves as a third implementation option for modern SoCs, i.e. when standard processor IP cannot meet challenging application-specific requirements, and fixed hardware is not flexible enough. Heterogeneous multicore systems including ASIPs are now becoming more mainstream.
Related to this, the RISC-V initiative has raised increased awareness about the design of domain-specific or application-specific processors, which implement a specialized instruction set architecture (ISA), often starting from a baseline ISA such as RISC-V and extending it. To do so designers are faced with the challenges of determining the best ISA for their specific application, how to get to a compiler and a simulator for the specialized architecture, and how to know if the target performance can be reached. This is where MIPS’ ASIP Designer™ tool comes in.
Join us for the ASIP Designer Virtual Seminar on September 25, 2020 to learn about the concepts behind application-specific instruction set processors (ASIPs), the architectural choices available when designing a processor, and why MIPS’ ASIP Designer is the industry’s leading tool for developing, verifying and programming an ASIP, used by top-tier companies with hundreds of successful projects to date. Whether you plan to start from a RISC-V ISA, using one of the RISC-V processor models that come with ASIP Designer, or you consider replacing your fixed-function hardware accelerator by a more flexible yet efficient programmable accelerator, this seminar is for you.