The MIPS ARC-V™ RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern.
The ARC-V RMX-100 processors are based on the RISC-V instruction set architecture (ISA) and feature a balanced 3-stage Harvard architecture pipeline that provides sufficient throughput. The ARC-V RMX-100 features up to 64KB of level 1 (L1) instruction cache and up to 2MB each of closely coupled instruction and data memories (CCM).
To enable easy software development, the ARC MetaWare Development Toolkit features a rich software library. The ARC-V RMX-100 processors maintain the high code density and offer excellent performance within a very small footprint.
To maximize PPA of ARC-V RMX Processor-based designs, a Fusion QuickStart Implementation Kit (QIK) that includes tool scripts, a baseline floorplan, design constraints and documentation, is available.
Highlights & Key Features
- RISC-V ISA 32-bit processors for ultra-low power embedded applications
- Base RV32E / RV32I ISA + optional extensions
- Single and double precision floating point
- High degree of configurability
- Support for custom instructions
- Support for 4KB to 64KB L1 instruction cache
- Support for up to 2 MB of closely coupled memories and direct mapping of peripherals
- Native Arm AMBA® AHB5™ and AXI5 interfaces
- Optional single and multicycle multiplier and HW divide module
- ECC support
- RISC-V AIA compliant interrupt handling
- N-Trace real-time trace debugging
- Easy programming support with MIPS Metaware C/C++ Compiler
- Broad third-party and open-source software development tools support
- Full compatibility with existing RISC-V code base
Product Details
| ARC-V RMX-100 Series IEEE754 compliant Single and/or Double Precision Floating Point Unit option | STARs | Subscribe |
| ARC-V RMX-100 ultra low-power embedded processor | STARs | Subscribe |
| ARC-V RMX-110-FS with ASIL-D support for functional safety embedded applications | STARs | Subscribe |
| This is an optional set of custom scalar uDSP extensions for ARC-V RMX-100 and RMX-110-FS | STARs | Subscribe |
| Description | ARC-V RMX-100 ultra low-power embedded processor |
| Name | dwc_arcv_rmx100_core |
| Version | 1.00a |
| ECCN | 3E991/NLR |
| STARs | Open and/or Closed STARs |
| myDesignWare | Subscribe for Notifications |
| Product Type | DesignWare Cores |
| Documentation | Show Documents Hide Documents DatabookAPEX Databook for RMX Processors (1.00a) ( PDF ) HAPS Reference Design Flow Databook for RMX Processors (1.00a) ( PDF ) Implementation GuideRMX-100 Implementation and Integration Guide (1.00a) ( PDF ) RMX-100 Implementation and Integration Guide (Beta) ( PDF ) Reference ManualRMX-100 Technical Reference Manual (1.00a) ( PDF ) RMX-100 Technical Reference Manual (Beta) ( PDF ) User GuideASIC RDF User Guide (1.00a) ( PDF ) |
| Toolsets | Qualified Toolsets |
| Download | dwc_arcv_rmx100_core |
| Product Code | J118-0 |