Oxford, United Kingdom – March 13th, 2023 – Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced with MIPS and Ashling a new 3-way collaboration to support developers across all aspects of RISC-V software development for advanced processor applications. Based on the Imperas reference models for the MIPS eVocore P8700 RISC-V […]
Prestigious Global Industry Accolades Honor Top Embedded Systems Innovations SAN JOSE, Calif., Feb. 28, 2023 — MIPS, a leading developer of highly scalable RISC processor IP, has been named an Embedded Award nominee for the company’s eVocore (™) P8700 multiprocessor system, the industry’s most scalable RISC-V CPU IP core. As part of the Embedded World
MIPS Named Embedded Award Nominee for eVocore P8700 Multiprocessor Read More »
Industry’s Highest Performance, Most Scalable RISC-V IP Core Already Adopted for Next-Generation Automotive Applications San Jose, Calif., Dec. 12, 2022 — As the shift toward RISC-V accelerates across industries, the open standard instruction set architecture (ISA) is ushering a new wave of innovation and collaboration. In an effort to help fuel this trend, MIPS, a
Mobileye Adopts New MIPS eVocore RISC-V CPUs; RISC-V Architecture to Help Drive Future of Vehicle Safety San Jose, Calif., December 12, 2022- MIPS, a leading developer of highly scalable RISC processor IP, announced it is continuing its partnership with Mobileye, in accelerating innovation in autonomous driving technologies and advanced driver-assistance systems (ADAS). As part of
Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models, Verification IP, and test suites Oxford, United Kingdom, December 7th, 2022 — Imperas Software Ltd., the leader in RISC-V simulation solutions, announced today that MIPS, a leading developer of highly scalable RISC processor
RISC-V Summit has always been the ideal venue to unveil new innovations that drive higher performance and greater scalability for today’s complex applications. And this year will be no different! MIPS will take to the FutureWatch stage at RISC-V Summit 2022, introducing industry media and analysts to an exciting new platform that is purpose-built for
We’re Getting Ready to Launch Something Big at RISC-V Summit 2022! Read More »
Architecture Will Accelerate Innovation in Open Computing SAN JOSE, Calif., Aug. 30, 2022 /PRNewswire/ — MIPS, a leading developer of highly scalable RISC processor IP, announced it is working with Intel to accelerate innovation in open computing. As part of this effort, MIPS’ eVocore is being incorporated into the new Intel® Pathfinder for RISC-V*, a
Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V Read More »
July 11th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface) for RISC-V processor verification with virtual peripherals to support asynchronous events and system level interrupts. Plus, the growing adoption of RVVI by many leading development teams that are driving the design innovations
Previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors SAN JOSE, Calif. – May 10, 2022 – MIPS, a leading developer of highly scalable RISC processor IP, announces its entrance to the RISC-V market, previewing the first products in its eVocore™ product lineup. The new eVocore P8700 and I8500 multiprocessor
MIPS Pivots to RISC-V with Best-In-Class Performance and Scalability Read More »
SILICON VALLEY, CA, USA – March 28, 2022. Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS RISC-V ISA based IP cores. RiscFree™ is Ashling’s Integrated Development Environment (IDE) including a compiler and debugger for RISC-V based development, and it now has support for MIPS RISC-V ISA based IP cores,
MIPS chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA compatible IP cores Read More »
