MIPS Blog
Innovation Starts at Product Inception
- May 1, 2025
Introducing the MIPS Atlas Portfolio for Physical AI
- March 4, 2025
Physical AI will enable the next generation of autonomous robots to sense the world around them, think to create a plan based on...
Introducing MIPS Sense data movement engines
- March 4, 2025
Autonomous platforms sense the world around them with a variety of inputs, from radar, lidar, and cameras, to gyroscopes, accelerometers, and atmospheric sensors....
Real-Time Intelligence for Physical AI at the Edge
- March 4, 2025
The age of physical AI is approaching, taking the virtual world of digital twins and move it into the physical world of autonomous...
Moving the World with MIPS M8500 Real-Time Compute Solutions
- March 4, 2025
The advent of physical AI promises to deliver autonomous platforms that are more able to operate in the changing world around them. Decisions...
The Shift-Left Approach to Software Development
- March 4, 2025
For years, the industry has advocated for “shifting left” in software development. This methodology allows software teams to begin their work earlier, leveraging...
Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- January 14, 2025
Introduction The rise of AI has unleashed an insatiable demand for faster, smarter, and more scalable data center networks. As GPUs and accelerators...
Scaling Out Deep Learning (DL) Inference and Training: Addressing Bottlenecks with Storage, Networking with RISC-V CPUs
Scale out DL inference or training is no longer just a compute problem. Networking and storage optimization are becoming more critical. This...
Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- November 19, 2024
The rise of opensource RISC-V CPU Instruction Set Architecture (ISA) has led many developers to consider migrating from existing popular computer architectures like...
Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- November 14, 2024
RISC-V International N-Trace Technical Group Milestone
- August 30, 2024
The market is experiencing a major shift to the RISC-V ISA and MIPS is helping to fuel this transition with high performance RISC-V...
The New MIPS – Solving Compute Where It Happens
- June 4, 2024
Timing, opportunity and geographic location matter in life – when we decide to do important things and where we decide to live and...
Whitepapers
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Auto Re-vectorization Whitepaper
The methodology was designed to systematically transform other vector/SIMD ISA (x86 AVX, ARM SVE/Neon, etc) intrinsic code into RISC-V Vector assembly and analyze its performance metrics. The procedure consists of first converting the input intrinsic code (other vector ISA) to LLVM Vector IR, then modifying the input ISA attributes to RISC-V Vector attributes, applying LLVM vector optimization passes (for a specific RISC-V Vector Processor) and finally lowering the optimized LLVM Vector IR to the target RISC-V Vector CPU assembly code.
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The Benefits of Hardware Multi-Threading
Increase Silicon Efficiency for Higher Data Processing with the Same Area and Power
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HyperFRAME Research
HyperFRAME Research delivers in depth research and insights across the global technology landscape, spanning everything from hyperscale public cloud to the mainframe and everything in between. HyperFRAME industry analysts have published their analysis of the MIPS Atlas portfolio and turnkey approach to Physical AI compute subsystems.
