A DMA controller improves efficiency by moving data around in a system without the involvement of the CPU. The µDMA controller is a fast, low energy optimized option for MIPS ARC® EM Processors to allow fast DMA transfers with low gate count and low power consumption. The µDMA engine is tightly coupled to the EM core interfaces to achieve low latency and cycle-efficient DMA transfers optimized to reduce energy. The closely coupled memory (CCM) interface supports DMA data transfer to and from ICCM0, ICCM1, DCCM or XY Memory, and a DMA peripheral interface is provided to allow external devices (such as a MIPS IC peripheral IP) to initiate DMA transfers. Each channel is assigned a separate request/acknowledge signal interface.
Highlights & Key Features
- Tightly coupled to the EM core interfaces for low latency, energy efficient DMA transfers
- 1 to 16 independent programmable DMA channels (configurable)
- User-programmable prioritization scheme for all channels
- Concurrent operation with the CPU
- Software and hardware triggered DMA transfers
- Two addressing modes
- Up to 5 data transfer modes (configurable down to 1)
- Internal and external interrupt support
Product Details
| Description | The uDMA controller for EM Processors is a programmable, small and low power memory access controller |
| Name | dwc_arc_em_udma |
| Version | 5.70b |
| ECCN | 3E991/NLR |
| STARs | Open and/or Closed STARs |
| myDesignWare | Subscribe for Notifications |
| Product Type | DesignWare Cores |
| Documentation | Show Documents Hide Documents DatasheetARC microDMA Controller for MIPS ARC EM Processors Datasheet ( PDF ) |
| Toolsets | Qualified Toolsets |
| Download | dwc_arc_em_udma |
| Product Code | B074-0 |