Overview
The MIPS ARC® HS44, HS46, and HS48 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications where high-performance and high clock speed are required. The cores can be clocked at up to 1.9 GHz in 16ff processes (worst case, single core, base configuration) and offer outstanding performance delivering 3.0 DMIPS/MHz and 5.2 CoreMark/MHz with a small area footprint and low power consumption.
The ARC HS44, HS46 and HS48 processors are based on the advanced ARCv2 instruction set architecture (ISA) and pipeline, which provides leadership power efficiency and code density. For applications requiring higher performance, dual- and quad-core versions of all three ARC HS4x processors are available.
The ARC HS44 features close coupled memory (CCM) and is optimized for use in applications where real-time, deterministic behavior is required. The HS46 is designed for high-performance embedded applications that require cache and includes all of the features of the HS44 plus support for up to 64K Level 1 (L1) instruction and data cache. The HS48 is designed for use in applications running Linux or SMP Linux. The HS48 has all of the features of the HS46 plus support for up to 8MB of L2 cache, as well as a Memory Management Unit (MMU) supporting a 40-bit physical address space and page sizes up to 16 megabytes (MBs).
The HS44, HS46 and HS48 are designed to be used in applications such as SSD controllers, home networking, automotive systems, smart appliances, and many other high-end embedded applications.
Highlights
- Dual-issue, 32-bit processor for high-performance embedded applications
- Deliver up to 5700 DMIPS and 9880 CoreMark per core at 1.9 GHz on 16ff (worst case conditions, single-core configuration)
- 3.0 DMIPS/MHz, 5.2 CoreMarks/ MHz (per core)
- Based on advanced ARCv2 ISA
- High degree of configurability
- Enhanced MMU (HS48) with 40-bit physical address and up to 16 MB page sizes
- Support for custom instructions
- Support for up to 16 MB of close coupled memory and direct mapping of peripherals
- Dual- and quad-core versions for higher performance
- Floating Point Unit (FPU) supporting single- and double-precision IEEE 754-compliant math operations
- Real-time Trace (RTT) provides real-time trace debugging features
- Easy performance upgrade from HS3x family – drop in replacement for HS3x
Licensable Options
- Memory Management Unit (MMU)
- L2 Cache
- Floating Point
- Memory Protection
- Mathematical Functions
- Debug
- Cluster DMA
Product Details
Products
| ARC HS44 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications | STARs | Subscribe |
| ARC HS44x2 dual-core version of dual-issue HS44 for embedded real-time applications | STARs | Subscribe |
| ARC HS44x4 quad-core version of dual-issue HS44 for real-time embedded applications | STARs | Subscribe |
| ARC HS46 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications | STARs | Subscribe |
| ARC HS46x2 dual-core version of dual-issue HS46 with I and D cache for high-performance embedded applications | STARs | Subscribe |
| ARC HS46x4 quad-core version of dual-issue HS46 with I and D cache for high-performance embedded applications | STARs | Subscribe |
| ARC HS48 32-bit, dual-issue processor with MMU, ARCv2 ISA, for embedded Linux applications | STARs | Subscribe |
| ARC HS48x2 dual-core version of dual-issue HS48 processor with MMU, ARCv2 ISA, for embedded Linux applications | STARs | Subscribe |
| ARC HS48x4 is quad-core version of dual-issue HS48 processor with MMU, ARCv2 ISA, for embedded Linux applications | STARs | Subscribe |
Downloads & Documentation
| Description | ARC HS44 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications |
| Name | dwc_arc_hs44_core |
| Version | 4.10a |
| ECCN | 3E991/NLR |
| STARs | Open and/or Closed STARs |
| myDesignWare | Subscribe for Notifications |
| Product Type | DesignWare Cores |
| Documentation |
Application Notes ARC HS4x Halt on Reset Behavior ( PDF )
Databook ARC HS APEX Databook (4.10a) ( PDF )
ARC HS4x Series Databook (4.10a) ( PDF )
ARC HS4x Series Databook (Beta) ( PDF )
ARC Trace Databook (4.10a) ( PDF )
ARC Trace Databook (Beta) ( PDF )
HAPS Reference Design Flow Databook (4.10a) ( PDF )
Datasheet MIPS ARC HS4x Datasheet ( PDF )
Implementation Guide ARC HS4x Implementation and Integration Guide (4.10a) ( PDF )
ARC HS4x Implementation and Integration Guide (Beta) ( PDF )
Reference Manual ARCv2 FPGA Synthesis Flow (4.10a) ( PDF )
ARCv2 ISA Programmer's Reference Manual for ARC HS3x and 4x Processors (Public Edition) ( PDF )
ARCv2 ISA Programmer's Reference Manual for ARC HS4x Processors (4.10a) ( PDF )
User Guide ARC MIPS ASIC Reference Design Flow User's Guide (4.10a) ( PDF )
|
| Toolsets | Qualified Toolsets |
| Download | dwc_arc_hs44_core |
| Product Code | C238-0 |
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