Learn From The Experts
Featuring technology experts, MIPS ASIP webinars and conferences give you access to a variety of topics around our ASIP portfolio. Watch them at your leisure.
Overview
| Event Type | Application | Title | Language |
|---|---|---|---|
| University Day 2025 | Edge AI & NPU | ASIP University Day 2025 Domain Specific Processor Design Using ASIP Designer | English |
| Webinar 2025 | 5G | -Specific Processors (ASIPs) for Wireless Communication SoCs | English |
| University Day 2024 | RISC-V & AI & Wireless & Cryptography | Domain-Specific Processor Design using ASIP Designer | English |
| Seminar 2024 | RISC-V & AI | ASIP Designer enables the creation of custom vector DSPs for AI | English |
| University Day 2023 | RISC-V & AI & Wireless & Cryptography | Domain-Specific Processor Design using ASIP Designer | English |
| Seminar | Low-Power Smart Vision and Post-Quantum Cryptography | Case Studies in Low-Power Smart Vision and Post-Quantum Cryptography Applications | English |
| Seminar | RISC-V Processor | Developing Your Own RISC-V Processor with Fast Architecture-Driven PPA Optimization | English |
| University Day 2022 | AI Accelerators | Domain-Specific Processor Design using ASIP Designer | English |
| Seminar | 5G | ASIPs for 5G Wireless SoCs | English |
| Webinar | SLAM | Designing ASIPs for Smart Vision Systems: A SLAM Case study | English |
| Seminar | AI | Extending RISC Processors into Flexible Accelerators using ASIP Designer | English |
| Seminar EU | RISC-V & AI | Domain-Specific Processor Design using ASIP Designer | English |
| University Day 2021 | AI & 5G | Domain-Specific Processor Design using ASIP Designer - Proceedings only | English |
| DCLS | Efficient Dual-Core Lock-Step Processor Design with ASIP Designer: An ST STxP5 Case Study | English | Seminar US |
| RISC-V & AI | Domain-Specific Processor Design using ASIP Designer | English | Seminar Japan |
| RISC-V & AI & Cryptography | ASIP開発ソリューション・セミナー2023 | Japanese | Webinar |
| SLAM | Designing ASIPs for Smart Vision Systems: A SLAM Case study | Japanese | Seminar Japan |
| ASIP開発ソリューション・セミナ2020 | ASIP Develop Solutions | Japanese | Seminar China |
| 5G | 面向无线通信SoC的专用处理器设计工具——ASIP Designer | Chinese | [[A|# |
| chinese | ]] Seminar China | Post-Quantum Cryptography 使用 ASIP Designer 将 RISC 处理器扩展为灵活的加速器 后量子密码学应用的案例研究 Extending RISC Processors into Flexible Accelerators using ASIP Designer Case Study in Post-Quantum Cryptography | Chinese |
| [[A|# | chinese | ]] Seminar China AI 使用 ASIP Designer 将 RISC 处理器扩展为灵活的加速器 Extending RISC Processors into Flexible Accelerators using ASIP Designer | Chinese |
| Webinar | RISC-V | Development of RISC-V Processor with Fast, Architecture-Driven, PPA Optimization | Chinese |
Domain Specific Processor Design Using ASIP Designer
The AI revolution and other domains, like data centers, advanced wireless communications, image and video processing, automated driving assistance, and post-quantum cryptography need more powerful architectures with higher performance. This is driving demand for heterogeneous multicore systems including specific instruction set processors (ASIPs). ASIPs have become a mainstream implementation option for modern SoCs, i.e. when standard processor IP cannot meet challenging -specific requirements, and fixed hardware is not flexible enough. This growth has driven many university projects and increased interest in initiatives like RISCV, which has significantly expanded beyond UC Berkeley. -Specific Processors (ASIPs) for Wireless Communication SoCs
ASIP
The transition from 4G to 5G brought a rethinking of architectural concepts in wireless SoCs. Traditional splits between general-purpose processors and hardwired datapaths are no longer sufficient. Discover how ASIPs are revolutionizing 5G SoC design by meeting high data rates, low latency requirements, and low power consumption, all while maintaining software programmability.
Domain-Specific Processor Design using ASIP Designer
At this informal event, you will hear from leading university teams about their ASIP design project results across various domains. Additionally, MIPS will provide a technical update on ASIP Designer with reference examples.
ASIP
introduces you to the ASIP Designer tool-suite. It features a tutorial and two case studies from AI domains. The tutorial introduces the typical architectural features needed to accelerate AI algorithms, such as specialization, SIMD, and VLIW, and how ASIP Designer supports them. The first case study demonstrates a SIMD/VLIW architecture with a RISC-V baseline processor for accelerating activation functions. The second case study shows a RISC-V based ASIP for medium-throughput convolutional neural networks (CNN) with programming support for TensorFlowLite for Microcontrollers (TFLM).
Domain-Specific Processor Design using ASIP Designer
At this informal event, leading university teams will present results from their ongoing ASIP projects in a variety of domains. MIPS will share insight on market trends, and provide a technical update on ASIP Designer along with reference examples.
Developing Your Own RISC-V Processor with Fast Architecture-Driven PPA Optimization
will cover two products from MIPS’ portfolio of industry leading tools: MIPS ASIP Designer and MIPS RTL MIPS Architect. These tools help designers create highly customized processors faster while meeting the desired PPA targets with confidence. The solutions facilitate the Synthesis-in-the-Loop design approach, both during earlier architectural design stages with processor model modifications and during RTL implementation. A real-world case study will highlight their interoperability and the results that can be achieved. [[A|/designware-ip/resources/webinars/developing-risc-v-processor-
Domain-Specific Processor Design using ASIP Designer
At this informal event, leading university teams present results from their ongoing ASIP projects in a variety of domains such as AI accelerators and smart vision systems. MIPS shares insight on market trends, and provide a technical update on ASIP Designer along with reference examples.
ASIPs for 5G Wireless SoCs
introduces you to the ASIP Designer tool-suite. It features two case studies. The first case study by Lund University presents an -specific vector processor for CNN based massive MIMO user terminal positioning. The ASIP contains a scalar RISC processor extended with a vector datapath and integrated accelerators. The second case study by MIPS shows an accelerator for 5G NR channel equalization. A RISC baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for MMSE channel equalization using Cholesky Decomposition. [[A|/designware-ip/resources/webinars/asip-5g-wireless-
Designing ASIPs for Smart Vision Systems: A SLAM Case Study
Understand the trend of software-defined acceleration in advanced camera systems based on depth sensing technology; See how the ASIP Designer tool suite enables you to design the correct ASIP architecture for such needs in a short period of time; Observe what is followed in the actual design of the SLAM architecture design trajectory, including tool-assisted architecture and hardware optimization
Extending RISC Processors into Flexible Accelerators using ASIP Designer
introduces you to the ASIP Designer tool-suite. It features two case studies from popular The first case study, by the University of Virginia, shows the design exploration for a RISC-V based accelerator for edge AI applications compiled from graph formalisms, combining TVM and ASIP Designer. Performance and design productivity gains are illustrated for example deep neural networks and for matrix-based math computations. The second case study, by MIPS, shows an accelerator for image signal processing. A RISC-V baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for stereo image matching.
Domain-Specific Processor Design using ASIP Designer
Learn more about the power of ASIPs, and how ASIP Designer™ makes them a reality. This covers the architectural options to choose from when designing an ASIP. Using examples from the extensive processor model library that comes with ASIP Designer, we explain the different concepts of parallelization and specialization, and the tradeoffs that come with it. includes demonstrations of ASIP Designer as well as an investigation of multiple example designs from the DSP, security, and AI domains. [[A|/designware-ip/resources/webinars/asip-
Domain-Specific Processor Design using ASIP Designer
At this informal event, leading university teams presented results from their ongoing ASIP projects in a variety of domains such as 5G baseband and AI accelerators. MIPS shared insight on market trends, and provided a technical update on ASIP Designer along with reference examples.
Efficient Dual Core LockStep Processor Design with ASIP Designer: An ST STxP5 Case Study
To face increasing demand in SoCs for Functional Safety and Security, ST is developing custom processors implementing mechanisms that satisfy ISO26262 safety requirements and protect program execution against physical attacks. In order to reduce the risk due to random faults and thus achieve high safety integrity, or to protect against physical attacks, logic duplication also called Dual Core LockStep (DCLS) is a commonly deployed method. This presentation will explain how and why ST involved the MIPS ASIP team in the development of a solution to increase the functional safety and security goals of the DCLS, and it will describe the process to generate the DCLS and its design results.
Domain-Specific Processor Design Using ASIP Designer
The Fastest Path to Making an Open ISA Your Own learn why domain-specific processors gain a lot of attention these days, and why MIPS’ ASIP Designer is the industry’s leading tool to design, implement, program and verify such specialized processors. [[A|/designware-ip/resources/webinars/asip-
ASIP開発ソリューション・セミナー2023
ムーアの法則やデナードが提唱したスケール則の減速により、アプリケーションに特化した命令セットを持つプロセッサ (ASIP：エイシップ) に対する興味が高まっています。 [[A|/ja-jp/japan/events/asip-
Designing ASIPs for Smart Vision Systems: A SLAM Case Study
スマートビジョンシステムに最適な特定用途向けプロセッサ設計開発：SLAMケーススタディ
ASIP Development Solutions
[[A|/ja-jp/japan/resources/asip-japan-
ASIP Seminar China 2025
从4G到5G的成功转换需要重新思考无线SoC中的核心架构的实现。通用可编程处理器（主要用于MAC层和更高层级的协议）与硬件数据通路（主要用于数字前端和基带处理）之间的传统划分已不复存在。设计人员需要引入专用处理器 (ASIP)，以满足5G的高数据速率、低延迟和低功耗要求，同时保持软件可编程性，以便快速适应和部署新功能。5G SoC可以包含多核 ASIP系统，其中不同的ASIP通过定制以实现5G框图中的特定部分，例如FFT、信道估计和均衡、交织或信道编码。各个ASIP可能具有高度定制的指令级和数据级 (SIMD) 并行性，并具有定制的功能单元和内存架构。 本次分享，将介绍新思科技ASIP Designer工具如何帮助客户在很短的时间内进行处理器架构探索、设计和优化，从而针对5G及更高版本协议，定制适合自身的最优的处理器架构。 [[A|https://apposcmf8kb5033.pc.xiaoe-tech.com/detail/l_68d27aa9e4b0694c5b315628/4?app_id=appoSCMf8kb5033&alive_mode=0&pro_id=& =2&fromH5=true]] Watch Now
Extending RISC Processors into Flexible Accelerators using ASIP Designer
使用 ASIP Designer 将 RISC 处理器扩展为灵活的加速器
Extending RISC processors into Flexible Accelerators using ASIP Designer
使用 ASIP Designer 将 RISC 处理器扩展为灵活的加速器
Development of RISC-V Processor with Fast, Architecture-Driven, PPA Optimization
如何快速开发定制化RISC-V处理器并实现PPA目标 [[A|/zh-cn/china/resources/asip-designer-rtl- This experience is in beta mode. Please double check responses for accuracy. NOTICE: You are interacting with an AI-powered chatbot that provides general information about MIPS, including its products and services, which may be incorrect or incomplete. In the event of any conflict or discrepancy, the terms of your applicable agreements supersede any information provided by this chatbot. These chats may be accessed by MIPS and its service providers to customize the experience and improve this tool, and your use of this chatbot is an agreement to that data processing activity.
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