The MIPS ARC® SEM Family includes performance-efficient, ultra-low power, compact security processors that enable designers to integrate security into their SoC to protect against logical, hardware and physical attacks.
The ARC SEM security processors are RISC cores based on the ARCv2 instruction set architecture (ISA), with the capability to closely couple memories and peripherals. They integrate security features ideally suited for a wide range of embedded applications and can be implemented as either a standalone secure core or a single core performing both secure and normal functions. ARC SEM processors include SecureShield™ technology to enable creation of a Trusted Execution Environment (TEE) to isolate multiple execution contexts and protect secure functions from software vulnerabilities in user code.
The ARC SEM processors also include protection from side-channel attacks, which rely on information from the physical implementation rather than exploiting a direct weakness in the security measures themselves. Side-channel resistance features include uniform instruction timing, timing randomization, and power randomization, which obfuscate security operations from potential hackers. Although the ARC SEM processors do not themselves include cryptographic algorithms, these features enable third-party software or software accelerated implementations of cryptography in high value target applications such as embedded SIM and smart meters without the area overhead of dedicated hardware engines. Refer to the separately licensable ARC CryptoPack Option for more information about software accelerated cryptographic implementations.
The ARC SEM family includes the SEM110 and the SEM120D processors. Both processors include the features listed above and the SEM120D adds a DSP instruction set and unified multiply/MAC unit. It is suited for applications requiring real-time processing and security functionality in the same core.
Secure Your IoT Device with Ultra-Low Power ARC Processors
Learn how DesignWare ARC Processors help secure your IoT design without an extra security core, keeping area and power consumption to a minimum. Please download the white paper “Securing the Internet of Things: An Architect’s Guide to Securing IoT Devices Using Hardware Rooted Processor Security”
Highlights & Key Features
- Performance-, power- and area-efficient security processors for embedded applications
- Secure privilege mode orthogonal to kernel/user mode
- Enhanced secure MPU with context ID for secure or normal operation
- Up to 16 configurable protected regions and per region scrambling capability
- Uniform instruction timing and timing/power randomization for side channel resistance
- In-line instruction scrambling to protect algorithms from reverse engineering or IP theft
- Data and instruction path integrity checking to prevent fault injection attacks
- Integrated watchdog timer detects system failures that can result from tampering and enables countermeasures
- Secure debug capability with user defined challenge/ response mechanism
- Ability to add secure custom instructions or co-processors in a trusted mode boosts performance and reduces power
Product Details
| Description | ARC SEM110 Security Processor for Low Power Embedded Applications |
| Name | dwc_arc_sem110_core |
| Version | 5.70b |
| ECCN | 3E991/NLR |
| STARs | Open and/or Closed STARs |
| myDesignWare | Subscribe for Notifications |
| Product Type | DesignWare Cores |
| Documentation | Show Documents Hide Documents DatabookARC EM APEX Databook (5.70a) ( HTML ) ARC EM APEX Databook (5.70b) ( PDF ) ARC SEM Databook (5.70b) ( PDF ) ARC Trace Databook (EM 5.70a) ( HTML ) ARC Trace Databook (EM 5.70b) ( PDF ) DatasheetARC Secure Subsystem Datasheet ( PDF ) Reference ManualARC SEM Programmers Reference (5.70b) ( PDF ) User GuideARC SEM Implementation and Integration Guide (5.70b) ( PDF ) ARC SEM Security Guidelines (5.70a) ( HTML ) ARC SEM Security Guidelines (5.70b) ( PDF ) ARCv2 FPGA Synthesis Flow (EM 5.70a) ( HTML ) ARCv2 FPGA Synthesis Flow (EM 5.70b) ( PDF ) MIPS ASIC Reference Design Flow User's Guide (EM 5.70a) ( HTML ) MIPS ASIC Reference Design Flow User's Guide (EM 5.70b) ( PDF ) White PaperRight-Sizing Your Cryptographic Processing Solution ( PDF ) |
| Toolsets | Qualified Toolsets |
| Download | dwc_arc_sem110_core |
| Product Code | C208-0 |
| Description | ARC SEM120D Security Processor with DSP for Low Power Embedded Applications |
| Name | dwc_arc_sem120d_core |
| Version | 5.70b |
| ECCN | 3E991/NLR |
| STARs | Open and/or Closed STARs |
| myDesignWare | Subscribe for Notifications |
| Product Type | DesignWare Cores |
| Documentation | Show Documents Hide Documents DatabookARC EM APEX Databook (5.70a) ( HTML ) ARC EM APEX Databook (5.70b) ( PDF ) ARC SEM Databook (5.70b) ( PDF ) ARC Trace Databook (EM 5.70a) ( HTML ) ARC Trace Databook (EM 5.70b) ( PDF ) Reference ManualARC SEM Programmers Reference (5.70b) ( PDF ) User GuideARC SEM Implementation and Integration Guide (5.70b) ( PDF ) ARC SEM Security Guidelines (5.70a) ( HTML ) ARC SEM Security Guidelines (5.70b) ( PDF ) ARCv2 FPGA Synthesis Flow (EM 5.70a) ( HTML ) ARCv2 FPGA Synthesis Flow (EM 5.70b) ( PDF ) MIPS ASIC Reference Design Flow User's Guide (EM 5.70a) ( HTML ) MIPS ASIC Reference Design Flow User's Guide (EM 5.70b) ( PDF ) White PaperRight-Sizing Your Cryptographic Processing Solution ( PDF ) |
| Toolsets | Qualified Toolsets |
| Download | dwc_arc_sem120d_core |
| Product Code | C209-0 |