This coming week, a ridiculous number of people will be in Las Vegas for the annual extravaganza that is CES. First held in 1967, and originally known as the Consumer Electronics Show, the event now covers so many technology segments and products that it’s either the show about nothing or everything, depending on your perspective. […]
So we had a little bit more going on last week compared to the holiday week before that, but certainly not enough to make me think we’d want to delay this any further. End result: 6.7 is (in number of commits: over 17k non-merge commits, with 1k+ merges) one of the largest kernel releases we’ve
Linux 6.7 release – Main changes, Arm, RISC-V, and MIPS architectures Read More »
MIPS Inc. is emerging as a significant RISC-V processor core licensor under its recently-appointed CEO Sameer Wasson. eeNews Europe interviewed Wasson to find out how he expects to navigate the choppy waters of a processor market in flux.
CEO interview: MIPS’ Sameer Wasson on a RISC-V reboot Read More »
MIPS Inc. (San Jose, Calif.) has recruited Drew Barbier and Brad Burgess to its leadership team, both formerly with RISC-V pioneer SiFive Inc. Barbier joins MIPS as vice president of products and Burgess as chief architect. The appointments follow that of Sameer Wasson, who joined the company as CEO in September 2023 (see MIPS to
MIPS recruits former senior SiFive execs to boost RISC-V play Read More »
Two former SiFive executives have joined the executive leadership team of semiconductor design company MIPS. MIPS, a company focused on the development of high-performance RISC-V compute IP, announced that Drew Barbier has joined as VP of products and Brad Burgess has been named chief architect.
Chip company MIPS poaches two SiFive execs for leadership team Read More »
Chip designer MIPS has picked up two former execs from SiFive in a bid to boost its RISC-V development efforts. MIPS, the company that created the processor architecture of the same name, is now looking to the RISC-V open instruction set architecture for new products under the eVocore name. The eVocore P8700 has been shipping
MIPS snags top SiFive brains to amp up RISC-V business Read More »
MIPS, a leading developer of high- performance RISC-V compute IP, today announced the addition of two semiconductor industry veterans to its leadership team. Drew Barbier joins the company as VP of Products and Brad Burgess has been named Chief Architect. Both executives join the MIPS Executive Leadership team.
MIPS Welcomes New Executives as Part of Company’s Growth and Expansion Read More »
In a strategic move poised to invigorate the RISC architecture processors domain, MIPS Inc., a groundbreaking company in the sector, has announced the appointment of two industry stalwarts to its leadership team. Drew Barbier and Brad Burgess, both notable figures from SiFive Inc., a RISC-V pioneer, have now joined the ranks of MIPS. Barbier has
MIPS Inc. Boosts Leadership Team, Eyes RISC-V Market Expansion Read More »
MIPS, a storied CPU IP core company with a tortuous business/management history, is writing a new chapter under the watch of new CEO Sameer Wasson, formerly an executive at Texas Instruments. Can he lift MIPS from oblivion to relevance and solid growth? Wasson’s first order of business is to explain to the world who MIPS
Sameer Wasson’s Vision for MIPS/RISC-V Read More »
If the U.S. government intends to curb China’s adoption of emerging RISC-V architecture to develop homegrown chips, it may be getting late. Last month, China’s Shandong University deployed a server cluster with RISC-V CPUs. The system has a total of 3,072 cores, with 48 nodes of 64-bit RISC-V CPUs.
China Deploys Massive RISC-V Server in Commercial Cloud Read More »
