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Scaling Out Deep Learning (DL) Inference and Training: Addressing Bottlenecks with Storage, Networking with RISC-V CPUs

  Scale out DL inference or training is no longer just a compute problem. Networking and storage optimization are becoming more critical. This is evident with a new addition to MLPerf standards with regards to storage. In this blog we briefly explore how RISC-V can help here. The increasing complexity and data demands of deep […]

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Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture

The rise of opensource RISC-V CPU Instruction Set Architecture (ISA) has led many developers to consider migrating from existing popular computer architectures like x86, Arm, MIPS and more to RISC-V CPU ISA. This transition offers various advantages, including an open-source framework and extensive community support. In this blog, we’ll explore typical migration strategies and considerations

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Unlocking the Power of Edge AI Through Efficient Data Movement

In today’s interconnected world, the advancement of Edge AI has revolutionized the way we process and analyze data. Edge AI brings intelligence closer to the device, enabling real-time decision making and reducing the need for centralized processing. However, one of the often overlooked aspects of Edge AI is the importance of efficient data movement. Efficient

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MIPS Launches New Strategic Focus and ReBrand: The Freedom to Innovate Compute

Today is an exciting day at MIPS as we launch a rebrand and strategic focus on giving our customers the Freedom to Innovate Compute. For years, when customers have needed more processing power and compute density, we’ve always gone back to the evolution of process nodes. Every few years, a new process node comes along

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