Author name: newmips

With its transition to RISC-V, MIPS is targeting the high-performance segment of the processor market, leveraging its differentiation in real-time features

MIPS is showing the first results of its pivot to the RISC-V architecture following the collapse of Wave Computing.

MIPS, a developer of RISC processor IP, is entering into the RISC-V market and has offered previews of its first products in its eVocore product line-up.

MIPS is dead, right? Well, there’s now very little done on the architecture itself, MIPS (the company) has decided to switch to RISC-V architecture, and unveiled the eVocore product lineup currently comprised of the eVocore P8700 and I8500 multiprocessor IP cores.

SAN JOSE, Calif., May 10, 2022 — MIPS, a leading developer of highly scalable RISC processor IP, announces its entrance to the RISC-V market, previewing the first products in its eVocore product lineup. The new eVocore P8700 and I8500 multiprocessor IP cores are the first MIPS products based on the RISC-V open instruction set architecture

MIPS Tech is no longer working on their MIPS CPU instruction set architecture but has been taking on RISC-V based designs. Today the company made the bold announcement for their new eVocore P8700 and I8500 multiprocessor IP cores that they offer “Best-In-Class Performance and Scalability.”

MIPS Tech is now not engaged on their MIPS CPU instruction set structure however has been taking up RISC-V based mostly designs. At this time the corporate made the daring announcement for his or her new eVocore P8700 and I8500 multiprocessor IP cores that they provide “Greatest-In-Class Efficiency and Scalability.”