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Design & Reuse: RISC-V Sees Significant Growth and Technical Progress in 2022 with Billions of RISC-V Cores in Market

Members across the ecosystem have continued to innovate with cutting-edge RISC-V hardware and software solutions. MIPS announced the availability of its first RISC-V IP core, the high performance and scalable eVocore P8700 multiprocessor. MIPS also partnered with Mobileye to accelerate next generation autonomous driving technologies and advanced driver assistance systems with MIPS’ eVocore P8700 RISC-V […]

Design & Reuse: RISC-V Sees Significant Growth and Technical Progress in 2022 with Billions of RISC-V Cores in Market Read More »

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MIPS Announces Availability of its first RISC-V IP core – the eVocore P8700 Multiprocessor

Industry’s Highest Performance, Most Scalable RISC-V IP Core Already Adopted for Next-Generation Automotive Applications San Jose, Calif., Dec. 12, 2022 — As the shift toward RISC-V accelerates across industries, the open standard instruction set architecture (ISA) is ushering a new wave of innovation and collaboration. In an effort to help fuel this trend, MIPS, a

MIPS Announces Availability of its first RISC-V IP core – the eVocore P8700 Multiprocessor Read More »

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MIPS Partners With Mobileye to Accelerate Next Generation Autonomous Driving Technologies and Advanced Driver Assistance Systems

Mobileye Adopts New MIPS eVocore RISC-V CPUs; RISC-V Architecture to Help Drive Future of Vehicle Safety San Jose, Calif., December 12, 2022- MIPS, a leading developer of highly scalable RISC processor IP, announced it is continuing its partnership with Mobileye, in accelerating innovation in autonomous driving technologies and advanced driver-assistance systems (ADAS). As part of

MIPS Partners With Mobileye to Accelerate Next Generation Autonomous Driving Technologies and Advanced Driver Assistance Systems Read More »

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MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors

Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models, Verification IP, and test suites Oxford, United Kingdom, December 7th, 2022 — Imperas Software Ltd., the leader in RISC-V simulation solutions, announced today that MIPS, a leading developer of highly scalable RISC processor

MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors Read More »

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We’re Getting Ready to Launch Something Big at RISC-V Summit 2022!

RISC-V Summit has always been the ideal venue to unveil new innovations that drive higher performance and greater scalability for today’s complex applications. And this year will be no different! MIPS will take to the FutureWatch stage at RISC-V Summit 2022, introducing industry media and analysts to an exciting new platform that is purpose-built for

We’re Getting Ready to Launch Something Big at RISC-V Summit 2022! Read More »

Intel Taps MIPS eVocore for Intel Pathfinder for RISC V new

Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V

Architecture Will Accelerate Innovation in Open Computing SAN JOSE, Calif., Aug. 30, 2022 /PRNewswire/ — MIPS, a leading developer of highly scalable RISC processor IP, announced it is working with Intel to accelerate innovation in open computing. As part of this effort, MIPS’ eVocore is being incorporated into the new Intel® Pathfinder for RISC-V*, a

Intel Taps MIPS eVocore for Intel Pathfinder for RISC-V Read More »

MIPS is thrilled to be part of Imperas Open Standard RISC V Verification Interface RVVI scaled

MIPS is thrilled to be part of Imperas’ Open Standard RISC-V Verification Interface (RVVI)

July 11th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface) for RISC-V processor verification with virtual peripherals to support asynchronous events and system level interrupts. Plus, the growing adoption of RVVI by many leading development teams that are driving the design innovations

MIPS is thrilled to be part of Imperas’ Open Standard RISC-V Verification Interface (RVVI) Read More »

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