Rebrand Reflects the Company’s Strategic Focus on Giving Customers the Freedom to Innovate Compute in the Automotive, Data Center and Embedded Markets. SAN JOSE, CA – January 09, 2024 – MIPS, a leading developer of efficient and configurable compute cores, today announced its strategic rebrand that is being unveiled at the Consumer Electronics Show (CES […]
MIPS Launches New Corporate Brand At CES 2024 Read More »
Watch the Video: At MIPS, we are giving our customers the freedom to innovate compute in the automotive, data center and embedded markets: the freedom to select an open architecture, break down system bottlenecks, and not be constrained by a single ISA. We are helping customers migrate their software code base with open source standards
MIPS: Freedom to Innovate Compute Read More »
The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled “Examining China’s Grand Strategy For RISC-V” is part of their China Brief segment and leans on the security concerns of RISC-V.
China Is All In on a RISC-V Future Read More »
This coming week, a ridiculous number of people will be in Las Vegas for the annual extravaganza that is CES. First held in 1967, and originally known as the Consumer Electronics Show, the event now covers so many technology segments and products that it’s either the show about nothing or everything, depending on your perspective.
So we had a little bit more going on last week compared to the holiday week before that, but certainly not enough to make me think we’d want to delay this any further. End result: 6.7 is (in number of commits: over 17k non-merge commits, with 1k+ merges) one of the largest kernel releases we’ve
Linux 6.7 release – Main changes, Arm, RISC-V, and MIPS architectures Read More »
MIPS Inc. is emerging as a significant RISC-V processor core licensor under its recently-appointed CEO Sameer Wasson. eeNews Europe interviewed Wasson to find out how he expects to navigate the choppy waters of a processor market in flux.
CEO interview: MIPS’ Sameer Wasson on a RISC-V reboot Read More »
MIPS Inc. (San Jose, Calif.) has recruited Drew Barbier and Brad Burgess to its leadership team, both formerly with RISC-V pioneer SiFive Inc. Barbier joins MIPS as vice president of products and Burgess as chief architect. The appointments follow that of Sameer Wasson, who joined the company as CEO in September 2023 (see MIPS to
MIPS recruits former senior SiFive execs to boost RISC-V play Read More »
Two former SiFive executives have joined the executive leadership team of semiconductor design company MIPS. MIPS, a company focused on the development of high-performance RISC-V compute IP, announced that Drew Barbier has joined as VP of products and Brad Burgess has been named chief architect.
Chip company MIPS poaches two SiFive execs for leadership team Read More »
Chip designer MIPS has picked up two former execs from SiFive in a bid to boost its RISC-V development efforts. MIPS, the company that created the processor architecture of the same name, is now looking to the RISC-V open instruction set architecture for new products under the eVocore name. The eVocore P8700 has been shipping
MIPS snags top SiFive brains to amp up RISC-V business Read More »
MIPS, a leading developer of high- performance RISC-V compute IP, today announced the addition of two semiconductor industry veterans to its leadership team. Drew Barbier joins the company as VP of Products and Brad Burgess has been named Chief Architect. Both executives join the MIPS Executive Leadership team.
MIPS Welcomes New Executives as Part of Company’s Growth and Expansion Read More »
