Live Demonstration of Synopsys ImperasFPM Models for MIPS Processors at Embedded World 2024 Showcases Collaboration for RISC-V-Based Designs SAN JOSE, CA – April 04, 2024 – MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc. to accelerate ecosystem enablement of MIPS RISC-V IP and […]
In today’s interconnected world, the advancement of Edge AI has revolutionized the way we process and analyze data. Edge AI brings intelligence closer to the device, enabling real-time decision making and reducing the need for centralized processing. However, one of the often overlooked aspects of Edge AI is the importance of efficient data movement. Efficient
Unlocking the Power of Edge AI Through Efficient Data Movement Read More »
MIPS, a leading developer of efficient and configurable compute cores, today announced the company’s global expansion with the launch of a new R&D center in Austin, TX, making this the second office expansion in Texas after Dallas. MIPS plans to tap into the growing AI engineering talent in Texas and continue to build deeper roots in the community by partnering with local universities and schools.
MIPS, a leading developer of efficient and configurable compute cores, today announced the company’s global expansion with the launch of a new R&D center in Austin, TX, making this the second office expansion in Texas after Dallas. MIPS plans to tap into the growing AI engineering talent in Texas and continue to build deeper roots in the community by partnering with local universities and schools.
RISC-V, the groundbreaking open and customizable instruction set architecture (ISA), is transforming the world of microprocessors. Its exceptional flexibility empowers developers to craft processors precisely suited for their needs, setting it apart as the go-to choice for a diverse range of devices, from energy-efficient IoT gadgets to powerful servers.
RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA Read More »
Memory safety problems, particularly when it comes to unsafe usage of pointers, are widespread and can cause significant security breaches. and consequent economic damage. CHERI provides a hardware solution by offering fine-grained memory protection.
What’s the Difference Between Conventional Memory Protection and CHERI? Read More »
MIPS this week used CES 2024 to announce its new strategic focus and at the same time rebrand, under a mission to “give back control” to designers looking to differentiate their compute architectures in a new AI-centric world, using the inherent benefits of the RISC-V architecture to enable that.
MIPS Aims to Give Back Control, for AI-Centric Compute Read More »
MIPS has been known for delivering low-power, high-performance embedded processor designs, but its MIPS architecture has been eclipsed by other RISC architectures like Arm and lately RISC-V. RISC-V developers are now MIPS’s target audience thanks to its RISC-V-based platforms. I talked with MIPS CEO, Sameer Wasson, about where MIPS is headed (see video above).
Another Major Player Shakes Up the RISC-V Arena Read More »
Sameer Wasson is passionate about RISC-V architecture and recently became CEO of MIPS to show the world how important an architecture it is. He uses words like “freedom” when talking about how MIPS and RISC-V can change how developers view the coming demands on software, especially as cars become software defined and where over-the-air updates
CES: MIPS CEO Sameer Wasson sees RISC-V as path to freedom Read More »
MIPS has been know for delivering low power, high performance embedded processor designs but its MIPS architecture has been eclipsed by other RISC architectures like Arm and lately RISC-V. RISC-V developers are now MIPS target audience as its primary platforms are now RISC-V-based.
Why is MIPS Putting its Primary Focus on RISC-V? Read More »
