Multicore RISC-V Designs for Smart Automotive Apps
A cluster of six MIPS P8700 RISC-V cores can be replicated up to 64 times to support 768 execution threads.
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Scaling Out Deep Learning (DL) Inference and Training: Addressing Bottlenecks with Storage, Networking with RISC-V CPUs
Scale out DL inference or training is no longer just a compute problem. Networking and storage optimization are becoming more critical. This is evident with a new addition to MLPerf standards with regards to storage. In this blog we briefly explore how RISC-V can help here. The increasing complexity and data demands of deep
Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
The rise of opensource RISC-V CPU Instruction Set Architecture (ISA) has led many developers to consider migrating from existing popular computer architectures like x86, Arm, MIPS and more to RISC-V CPU ISA. This transition offers various advantages, including an open-source framework and extensive community support. In this blog, we’ll explore typical migration strategies and considerations
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Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
Do you need more compute elements? Do you need more memory? Do you need more cache? Last week we announced the MIPS P8700, the industry’s first AI-enabled RISC-V automotive CPU for ADAS and autonomous vehicles. The MIPS P8700 gives you the freedom to choose how to solve your problem.
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AI-Enabled RISC-V Cores Target ASIL B Automotive Apps
The MIPS P8700 RISC-V core, which implements a RISC-V ISA, aims at ASIL B and ISO 26262 functional safety.
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MIPS releases RISC-V CPU for autonomous vehicles
MIPS released its P8700 CPU based on the RISC-V computing architecture to target driver assistance and autonomous vehicle applications.
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MIPS Releases P8700, Industry’s First High-Performance AI-Enabled RISC-V Automotive CPU for ADAS and Autonomous Vehicles
MIPS, a leading developer of efficient and configurable IP compute cores, will showcase the company’s latest innovations and suite of system deployments at Computex 2024.
RISC-V International N-Trace Technical Group Milestone
The market is experiencing a major shift to the RISC-V ISA and MIPS is helping to fuel this transition with high performance RISC-V cores, including debug, trace and performance tools enabling the tools ecosystem. The commercial success of the MIPS architecture can, to some degree, be attributed to deploying advanced debug, trace and performance monitoring
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Addressing AI While Keeping the MIPSiness In MIPS
MIPS, now targeting AI applications for its application-specific data movement cores, is evolving with a careful eye on its strengths.
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Sameer Wasson: Have a Steady Hand, Don’t be Distracted
In this episode of Silicon Grapevine, we talk to MIPS CEO Sameer Wasson about the experience of going from an intern doing FPGA programming
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