Scale out DL inference or training is no longer just a compute problem. Networking and storage optimization are becoming more critical. This is evident with a new addition to MLPerf standards with regards to storage. In this blog we briefly explore how RISC-V can help here. The increasing complexity and data demands of deep […]
The rise of opensource RISC-V CPU Instruction Set Architecture (ISA) has led many developers to consider migrating from existing popular computer architectures like x86, Arm, MIPS and more to RISC-V CPU ISA. This transition offers various advantages, including an open-source framework and extensive community support. In this blog, we’ll explore typical migration strategies and considerations
Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture Read More »
Do you need more compute elements? Do you need more memory? Do you need more cache? Last week we announced the MIPS P8700, the industry’s first AI-enabled RISC-V automotive CPU for ADAS and autonomous vehicles. The MIPS P8700 gives you the freedom to choose how to solve your problem.
Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700 Read More »
The MIPS P8700 RISC-V core, which implements a RISC-V ISA, aims at ASIL B and ISO 26262 functional safety.
AI-Enabled RISC-V Cores Target ASIL B Automotive Apps Read More »
MIPS released its P8700 CPU based on the RISC-V computing architecture to target driver assistance and autonomous vehicle applications.
MIPS releases RISC-V CPU for autonomous vehicles Read More »
MIPS, a leading developer of efficient and configurable IP compute cores, will showcase the company’s latest innovations and suite of system deployments at Computex 2024.
The market is experiencing a major shift to the RISC-V ISA and MIPS is helping to fuel this transition with high performance RISC-V cores, including debug, trace and performance tools enabling the tools ecosystem. The commercial success of the MIPS architecture can, to some degree, be attributed to deploying advanced debug, trace and performance monitoring
RISC-V International N-Trace Technical Group Milestone Read More »
MIPS, now targeting AI applications for its application-specific data movement cores, is evolving with a careful eye on its strengths.
Addressing AI While Keeping the MIPSiness In MIPS Read More »
In this episode of Silicon Grapevine, we talk to MIPS CEO Sameer Wasson about the experience of going from an intern doing FPGA programming
Sameer Wasson: Have a Steady Hand, Don’t be Distracted Read More »
Timing, opportunity and geographic location matter in life – when we decide to do important things and where we decide to live and work.
The New MIPS – Solving Compute Where It Happens Read More »
