Author name: newmips

The rise of opensource RISC-V CPU Instruction Set Architecture (ISA) has led many developers to consider migrating from existing popular computer architectures like x86, Arm, MIPS and more to RISC-V CPU ISA. This transition offers various advantages, including an open-source framework and extensive community support. In this blog, we’ll explore typical migration strategies and considerations […]

Do you need more compute elements? Do you need more memory? Do you need more cache? Last week we announced the MIPS P8700, the industry’s first AI-enabled RISC-V automotive CPU for ADAS and autonomous vehicles. The MIPS P8700 gives you the freedom to choose how to solve your problem.

The market is experiencing a major shift to the RISC-V ISA and MIPS is helping to fuel this transition with high performance RISC-V cores, including debug, trace and performance tools enabling the tools ecosystem. The commercial success of the MIPS architecture can, to some degree, be attributed to deploying advanced debug, trace and performance monitoring

Timing, opportunity and geographic location matter in life – when we decide to do important things and where we decide to live and work. It turns out these factors are also important in solving the biggest compute challenges our industry is facing at this time. I am personally very thankful for joining the MIPS leadership