If the U.S. government intends to curb China’s adoption of emerging RISC-V architecture to develop homegrown chips, it may be getting late. Last month, China’s Shandong University deployed a server cluster with RISC-V CPUs. The system has a total of 3,072 cores, with 48 nodes of 64-bit RISC-V CPUs.
China Deploys Massive RISC-V Server in Commercial Cloud Read More »
The recent growth in RISC-V interest and adoption is hard to deny, and MIPS, a developer of high-performance RISC-V compute IP, is looking to grow right along with the rising tide.
Embedded Computing Design: MIPS Plans Expansion, Pulls New CEO from TI Read More »
MIPS is using an FPGA platform from Siemens Digital Industries Software to accelerate software development for its eVocore P8700 RISC-V multiprocessor.
MIPS taps Siemens FPGA for RISC-V CPU roll out Read More »
Even though the company had telegraphed its big move, MIPS’s adoption of the RISC-V ISA for its future processor cores hit me like a ton of bricks.
Electronic Engineering: MIPS Rolls Out Its First RISC-V Processor Core Read More »
MIPS announced that Mobileye adopted its eVocore P8700 for the next-generation EyeQ SoC for autonomous driving and advanced driver assistance systems (ADAS).
EE Times: RISC-V Summit 2022: All Your CPUs Belong to Us Read More »
RISC-V is everywhere. RISC-V is redefining computing. And that’s not just for this quarter. This is for the next era of computing.
All About Circuits: “RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes Read More »
MIPS, a developer of scalable RISC processor IP, has announced the availability of the eVocore P8700, said to be the industry’s highest performance, most scalable RISC-V multiprocessor IP.
New Electronics: MIPS makes first RISC-V IP core available Read More »
MIPS has announced the availability of the eVocore P8700, the industry’s highest-performance, most scalable RISC-V multiprocessor IP. The P8700 has already been licensed for applications including automotive driver assistance systems (ADAS) and autonomous driving.
EE World Online: Scalable RISC-V multiprocessor IP promotes efficient SoC uses Read More »
Perhaps the biggest news at the RISC-V Summit came from MIPS. The story of MIPS is as full of twists, turns, and surprises as any you get in Silicon Valley.
Forbes: MIPS Joins The RISC-V Gang Read More »
Members across the ecosystem have continued to innovate with cutting-edge RISC-V hardware and software solutions. MIPS announced the availability of its first RISC-V IP core, the high performance and scalable eVocore P8700 multiprocessor. MIPS also partnered with Mobileye to accelerate next generation autonomous driving technologies and advanced driver assistance systems with MIPS’ eVocore P8700 RISC-V
