MIPS, a leading developer of high- performance RISC-V compute IP, today announced the addition of two semiconductor industry veterans to its leadership team. Drew Barbier joins the company as VP of Products and Brad Burgess has been named Chief Architect. Both executives join the MIPS Executive Leadership team.
MIPS Welcomes New Executives as Part of Company’s Growth and Expansion Read More »
In a strategic move poised to invigorate the RISC architecture processors domain, MIPS Inc., a groundbreaking company in the sector, has announced the appointment of two industry stalwarts to its leadership team. Drew Barbier and Brad Burgess, both notable figures from SiFive Inc., a RISC-V pioneer, have now joined the ranks of MIPS. Barbier has
MIPS Inc. Boosts Leadership Team, Eyes RISC-V Market Expansion Read More »
MIPS, a storied CPU IP core company with a tortuous business/management history, is writing a new chapter under the watch of new CEO Sameer Wasson, formerly an executive at Texas Instruments. Can he lift MIPS from oblivion to relevance and solid growth? Wasson’s first order of business is to explain to the world who MIPS
Sameer Wasson’s Vision for MIPS/RISC-V Read More »
If the U.S. government intends to curb China’s adoption of emerging RISC-V architecture to develop homegrown chips, it may be getting late. Last month, China’s Shandong University deployed a server cluster with RISC-V CPUs. The system has a total of 3,072 cores, with 48 nodes of 64-bit RISC-V CPUs.
China Deploys Massive RISC-V Server in Commercial Cloud Read More »
The recent growth in RISC-V interest and adoption is hard to deny, and MIPS, a developer of high-performance RISC-V compute IP, is looking to grow right along with the rising tide.
Embedded Computing Design: MIPS Plans Expansion, Pulls New CEO from TI Read More »
MIPS is using an FPGA platform from Siemens Digital Industries Software to accelerate software development for its eVocore P8700 RISC-V multiprocessor.
MIPS taps Siemens FPGA for RISC-V CPU roll out Read More »
Even though the company had telegraphed its big move, MIPS’s adoption of the RISC-V ISA for its future processor cores hit me like a ton of bricks.
Electronic Engineering: MIPS Rolls Out Its First RISC-V Processor Core Read More »
MIPS announced that Mobileye adopted its eVocore P8700 for the next-generation EyeQ SoC for autonomous driving and advanced driver assistance systems (ADAS).
EE Times: RISC-V Summit 2022: All Your CPUs Belong to Us Read More »
RISC-V is everywhere. RISC-V is redefining computing. And that’s not just for this quarter. This is for the next era of computing.
All About Circuits: “RISC-V is Inevitable”—A Tale of Two RISC-V Summit Keynotes Read More »
MIPS, a developer of scalable RISC processor IP, has announced the availability of the eVocore P8700, said to be the industry’s highest performance, most scalable RISC-V multiprocessor IP.
New Electronics: MIPS makes first RISC-V IP core available Read More »
