In the News

MIPS has announced that it has expanded its collaboration with Synopsys to accelerate ecosystem enablement of MIPS RISC-V IP and their customer’s ability to innovate compute without constraints.

The Japanese government approved $3.9 billion in funding for chipmaker Rapidus to expand its foundry business, of which 10% will be invested in advanced packaging. This is in addition to the previously announced $2.18 billion in funding. In a meeting next week, the U.S. and Japan are expected to cooperate on increasing semiconductor development and trade in an effort to reduce dependence on China. The announcement comes amid continuing tensions between China and the U.S. over trade sanctions in advanced semiconductor equipment and materials.

MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc. to accelerate ecosystem enablement of MIPS RISC-V IP and their customer’s ability to innovate compute without constraints. MIPS will showcase MIPS’ RISC-V IP Core technology utilizing the Synopsys ImperasFPM Fast Processor Models and the Synopsys ImperasPDK Processor Development Kit software simulation tools at embedded world 2024.

MIPS, a leading developer of efficient and configurable compute cores, today announced the company’s global expansion with the launch of a new R&D center in Austin, TX, making this the second office expansion in Texas after Dallas. MIPS plans to tap into the growing AI engineering talent in Texas and continue to build deeper roots in the community by partnering with local universities and schools.

RISC-V, the groundbreaking open and customizable instruction set architecture (ISA), is transforming the world of microprocessors. Its exceptional flexibility empowers developers to craft processors precisely suited for their needs, setting it apart as the go-to choice for a diverse range of devices, from energy-efficient IoT gadgets to powerful servers.

Memory safety problems, particularly when it comes to unsafe usage of pointers, are widespread and can cause significant security breaches. and consequent economic damage. CHERI provides a hardware solution by offering fine-grained memory protection.

MIPS this week used CES 2024 to announce its new strategic focus and at the same time rebrand, under a mission to “give back control” to designers looking to differentiate their compute architectures in a new AI-centric world, using the inherent benefits of the RISC-V architecture to enable that.

MIPS has been known for delivering low-power, high-performance embedded processor designs, but its MIPS architecture has been eclipsed by other RISC architectures like Arm and lately RISC-V. RISC-V developers are now MIPS’s target audience thanks to its RISC-V-based platforms. I talked with MIPS CEO, Sameer Wasson, about where MIPS is headed (see video above).

Sameer Wasson is passionate about RISC-V architecture and recently became CEO of MIPS to show the world how important an architecture it is. He uses words like “freedom” when talking about how MIPS and RISC-V can change how developers view the coming demands on software, especially as cars become software defined and where over-the-air updates

MIPS has been know for delivering low power, high performance embedded processor designs but its MIPS architecture has been eclipsed by other RISC architectures like Arm and lately RISC-V. RISC-V developers are now MIPS target audience as its primary platforms are now RISC-V-based.