MIPS Sub-Systems – More than a Core
A foundation of compute DNA built over decades with billions of units shipped
Bring Your Own Accelerators
Flexible Integration
Coherent Through Coherence Manager Fabric or Connect Direct to CPU
Coherent Through Coherence Manager Fabric or Connect Direct to CPU
RISC-V Core
RISC-V Multi-threading
Custom Instructions
Virtualization
Custom Instructions
Virtualization
Debug and Trace
RISC-V Compliant
Multi-Core Debug and Trace
Multi-Core Debug and Trace
Interrupt Controller
RISC-V AIA Compliant
Core and Cluster
Core and Cluster
Coherent Last Level Cache
Coherent Across Cores and Accelerators
Coherent Connections to the Rest of the System
Directory-based
Coherent Connections to the Rest of the System
Directory-based
Coherence Manager
Heterogenous Core and Accelerator Mix
Power Management
Connect to Coherent and Non-coherent System Fabrics
Power Management
Connect to Coherent and Non-coherent System Fabrics
RISC-V Processor Offerings
P8700 Series
- 4-wide Out-of-order
- 2-way Simultaneous Multi-threading
- Up to 8 Cores per Cluster
- Automotive Capable ASIL-B
I8500 Series
- Triple-issue In-order
- Up to 4-way Simultaneous Multi-threading
- Up to 8 Cores per Cluster
- Automotive Capable ASIL-B
Resources
Helping Customers Jump Start MIPS Designs
Get started on your design with MIPS CPUs! Learn more about the growing ecosystem of tools and software supporting our family of RISC-V CPUs.
Latest Blog
Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
The rise of opensource RISC-V CPU Instruction Set Architecture (ISA) has led many developers to consider migrating from existing popular computer architectures like x86, Arm, MIPS and more to RISC-V
Download the Whitepaper
The Benefits of Hardware Multi-Threading
Increase Silicon Efficiency for Higher Data Processing with the Same Area and Power
Read More
Resources
Helping Customers Jump Start MIPS Designs
Get started on your design with MIPS CPUs! Learn more about the growing ecosystem of tools and software supporting our family of RISC-V CPU cores.
Project Exploration
Integration & Support
Bringing Differentiation to RISC-V
High-performance, highly efficient CPUs built on open industry standards, with MIPS’ proven architectural differentiators.
Efficient
Faster Computation Within Power & Capacity Constraints.Configurable
For Specific Design Requirements.Scalable
MIPS’ unique multi-threading capabilities enable multiple software threads to efficiently execute in parallel, bringing significant cost and power advantages.Open
Built on RISC-V for Unprecedented Freedom & Innovation.Safe & Reliable
Functional Safety and RAS Architecture.Proven
In Billions of Devices (over 8.5B MIPS-based Devices Shipped).Design and Innovate with MIPS Today
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