MIPS Atlas Explorer unlocks the first insights of the Atlas portfolio
Building innovative new products requires a detailed and comprehensive understanding of the target use cases. Building a visionary new platform with cutting-edge capabilities at the right time can deliver market success, capturing the value of emerging markets such as physical AI and sovereign manufacturing initiatives.
MIPS Atlas Explorer leans into the shift-left methodology of virtual platforms and takes the concept inside the chip – to pre-silicon IP exploration and evaluation. Following our announcement of the Atlas portfolio in March, customers can now access two of our platform IP products for their evaluation and software optimization activities.
The first two products available through Atlas Explorer are the MIPS M8500 high-performance microcontroller platform for ultra-low latency control loop applications; and the MIPS I8500 deterministic data processing engine platform for efficient deterministic data processing. Both platforms are based on RISC-V profiles, enhanced with custom MIPS extensions and μarchitecture innovations.
MIPS Multithreading for Real-Time Applications
Both the MIPS M8500 and I8500 platform IPs feature MIPS multithreading capabilities, with the ability to execute 4 threads per core. Uniquely, the MIPS M8500 platform introduces MIPS real-time multithreading (RTMT) to enable a single-core microcontroller to rapidly process events – even in sub-10μs control-loop algorithms. Real-time multithreading enables the M8500 able to manage motor control, digital power conversion, battery management and other control algorithms with high performance and minimized context switch penalties, all while being easy to program and simple to adopt. More details on the M8500 can be found here: Link.
MIPS Multithreading for Efficient Data Processing
As mentioned, the MIPS I8500 platform also delivers multithreading capabilities with up to 4 threads per core. This implementation of simultaneous multithreading enables deeply efficient data processing, offering up to 60% better performance-per-area1 (PPA). The I8500 delivers low-latency and deterministic data access, well-suited for automotive or industrial gateways, communications infrastructure, and datacenter infrastructure applications. More details on the I8500 can be found here: Link
Unlocking Innovation with Atlas Explorer
The first release of Atlas Explorer is a major step forward for MIPS, delivering access to platform IP ahead of silicon availability for evaluation, and we will ship regular updates to support our customers adoption and introduce new features. The key features of Atlas Explorer, described below, enable the crucial insights into MIPS platform IP running customer workloads needed for smooth and easy adoption into new products.
Report Filtering, Saving, and Sharing
Performance optimization is a team sport. Atlas Explorer’s custom filters let you zoom in on critical hotspots, save report configurations for side‑by‑side comparisons, and share views with teammates or domain experts. No rebuilds necessary, no cumbersome environment or tool mismatches.
Summary Reports
At a glance, Summary Reports surface key performance metrics across your entire workload. Perfect for comparing multiple experiments, they quantify throughput and efficiency. Instrument your code with up to five Regions of Interest (ROIs), and you’ll get separate summary reports for each ROI, enabling focused analysis.
Regions of Interest
These mark critical code sections with our provided C macros and isolate them into distinct performance buckets. Selecting up to five ROI’s per program enables you to target optimizations without drowning in data.
Executable & Linkable Format Data Reporting
The Executable & Linkable Format (ELF) Data Report extracts three critical views from your ELF binaries. ELF/Headers show general header information. ELF/Section Info shows start/end addresses and sizes for each section in target memory. ELF/Section Map is a pie chart visualizing each section’s memory footprint, making layout differences across experiments immediately obvious.
Function Summary & Explorer
Aggregated function‑level performance stats give you cumulative metrics across all calls. Clicking ‘Goto Source’ in any report opens the Function Explorer, which presents three synchronized panels: a list of functions, the source code (if available), and disassembly annotated with performance data.
Instruction Cost Tile-Map
Visualize the most expensive instructions within your ROI. Each tile is sized by total cycle cost. Hover for cycle counts, disassembly, and quick access to the Function Explorer.
Memory Access & Consumption Graphs
Memory Access shown as a bubble represents a load or store and is sized by cycle cost. This makes spotting cache misses and stalls a breeze. The Memory Consumption Graph shows bandwidth metrics (bytes loaded/stored, unique addresses, and calculated throughput) over time, dynamically re-binned as you zoom.
Instructions Per Cycle Over Time
Track average Instructions Per Cycle (IPC) from simulation start, revealing performance dips or peaks within your workload.
Early Access Features
Beyond the VS Code extension, we’re also releasing a Python library to script experiments and automate continuous integration and continuous development (CI/CD) regressions. Continuously tracking the performance for key kernels and system components will turn optimization efforts from a last‑minute scramble into an integral part of your development workflow.
Additionally, you’ll find an instruction trace report for ordered execution dumps and a customized Trace Viewer provided to capture feedback and guide future enhancements.
What’s Next
We’re gearing up to support multi‑threaded performance reports and selective trace capture in operating‑system contexts, extending analysis beyond bare‑metal code to processes, threads, and execution modes. Reach out to learn more about MIPS Atlas platform IP and Atlas Explorer, here: Link.
